From patchwork Wed May 3 12:23:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiri Slaby X-Patchwork-Id: 98487 Delivered-To: patch@linaro.org Received: by 10.140.89.200 with SMTP id v66csp29224qgd; Wed, 3 May 2017 05:25:47 -0700 (PDT) X-Received: by 10.99.44.209 with SMTP id s200mr39443124pgs.25.1493814251486; Wed, 03 May 2017 05:24:11 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a65si20209570pgc.165.2017.05.03.05.24.11; Wed, 03 May 2017 05:24:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752069AbdECMYK (ORCPT + 6 others); Wed, 3 May 2017 08:24:10 -0400 Received: from mx2.suse.de ([195.135.220.15]:38575 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752075AbdECMXl (ORCPT ); Wed, 3 May 2017 08:23:41 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 066C3AD48; Wed, 3 May 2017 12:23:40 +0000 (UTC) From: Jiri Slaby To: stable@vger.kernel.org Cc: Corey Minyard , David Daney , linux-mips@linux-mips.org, Ralf Baechle , Julia Lawall , Jiri Slaby Subject: [patch added to 3.12-stable] MIPS: Fix crash registers on non-crashing CPUs Date: Wed, 3 May 2017 14:23:19 +0200 Message-Id: <20170503122327.12095-41-jslaby@suse.cz> X-Mailer: git-send-email 2.12.2 In-Reply-To: <20170503122327.12095-1-jslaby@suse.cz> References: <20170503122327.12095-1-jslaby@suse.cz> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Corey Minyard This patch has been added to the 3.12 stable tree. If you have any objections, please let us know. -- 2.12.2 =============== commit c80e1b62ffca52e2d1d865ee58bc79c4c0c55005 upstream. As part of handling a crash on an SMP system, an IPI is send to all other CPUs to save their current registers and stop. It was using task_pt_regs(current) to get the registers, but that will only be accurate if the CPU was interrupted running in userland. Instead allow the architecture to pass in the registers (all pass NULL now, but allow for the future) and then use get_irq_regs() which should be accurate as we are in an interrupt. Fall back to task_pt_regs(current) if nothing else is available. Signed-off-by: Corey Minyard Cc: David Daney Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13050/ Signed-off-by: Ralf Baechle Cc: Julia Lawall Signed-off-by: Jiri Slaby --- arch/mips/kernel/crash.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/mips/kernel/crash.c b/arch/mips/kernel/crash.c index 93aa302948d7..c68312947ed9 100644 --- a/arch/mips/kernel/crash.c +++ b/arch/mips/kernel/crash.c @@ -15,12 +15,22 @@ static int crashing_cpu = -1; static cpumask_t cpus_in_crash = CPU_MASK_NONE; #ifdef CONFIG_SMP -static void crash_shutdown_secondary(void *ignore) +static void crash_shutdown_secondary(void *passed_regs) { - struct pt_regs *regs; + struct pt_regs *regs = passed_regs; int cpu = smp_processor_id(); - regs = task_pt_regs(current); + /* + * If we are passed registers, use those. Otherwise get the + * regs from the last interrupt, which should be correct, as + * we are in an interrupt. But if the regs are not there, + * pull them from the top of the stack. They are probably + * wrong, but we need something to keep from crashing again. + */ + if (!regs) + regs = get_irq_regs(); + if (!regs) + regs = task_pt_regs(current); if (!cpu_online(cpu)) return;