From patchwork Fri Jun 18 15:12:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 463833 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 043EEC49EA3 for ; Fri, 18 Jun 2021 15:30:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E512A610C7 for ; Fri, 18 Jun 2021 15:29:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235500AbhFRPcH (ORCPT ); Fri, 18 Jun 2021 11:32:07 -0400 Received: from mga01.intel.com ([192.55.52.88]:7103 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235285AbhFRPb2 (ORCPT ); Fri, 18 Jun 2021 11:31:28 -0400 IronPort-SDR: MgQ5ZCxjNAFS7/vz0kphj771n7b1AugnoPbXZd2t75njCz+5yuxf4+pHRysSA6Ya93YmzjFJy4 XAWNFhnIsu2Q== X-IronPort-AV: E=McAfee;i="6200,9189,10019"; a="228099639" X-IronPort-AV: E=Sophos;i="5.83,284,1616482800"; d="scan'208";a="228099639" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2021 08:27:38 -0700 IronPort-SDR: r8HS9NGeR6AV/PCqnu0qtWuyQ4OrVqc1qFvOvO1v+K3Y7Cnl5BNYtJapsKTskIEujVzKl+tTia q9m/u86F77+A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,284,1616482800"; d="scan'208";a="405004810" Received: from otc-lr-04.jf.intel.com ([10.54.39.41]) by orsmga006.jf.intel.com with ESMTP; 18 Jun 2021 08:27:32 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, linux-kernel@vger.kernel.org Cc: acme@kernel.org, jolsa@redhat.com, namhyung@kernel.org, ak@linux.intel.com, Kan Liang , stable@vger.kernel.org Subject: [PATCH 2/3] perf/x86/intel: Add more events requires FRONTEND MSR on Sapphire Rapids Date: Fri, 18 Jun 2021 08:12:53 -0700 Message-Id: <1624029174-122219-3-git-send-email-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624029174-122219-1-git-send-email-kan.liang@linux.intel.com> References: <1624029174-122219-1-git-send-email-kan.liang@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Kan Liang On Sapphire Rapids, there are two more events 0x40ad and 0x04c2 which rely on the FRONTEND MSR. If the FRONTEND MSR is not set correctly, the count value is not correct. Update intel_spr_extra_regs[] to support them. Fixes: 61b985e3e775 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids") Signed-off-by: Kan Liang Cc: stable@vger.kernel.org --- arch/x86/events/intel/core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index d39991b..e442b55 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -280,6 +280,8 @@ static struct extra_reg intel_spr_extra_regs[] __read_mostly = { INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), + INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), + INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), EVENT_EXTRA_END };