From patchwork Fri Jan 17 18:19:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: thermal-bot for Julien Panis X-Patchwork-Id: 233658 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D4F8C33C9E for ; Fri, 17 Jan 2020 18:19:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 638AD20748 for ; Fri, 17 Jan 2020 18:19:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729236AbgAQSTU (ORCPT ); Fri, 17 Jan 2020 13:19:20 -0500 Received: from Galois.linutronix.de ([193.142.43.55]:57232 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726973AbgAQSTT (ORCPT ); Fri, 17 Jan 2020 13:19:19 -0500 Received: from [5.158.153.53] (helo=tip-bot2.lab.linutronix.de) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1isWD9-00068R-0p; Fri, 17 Jan 2020 19:19:11 +0100 Received: from [127.0.1.1] (localhost [IPv6:::1]) by tip-bot2.lab.linutronix.de (Postfix) with ESMTP id 9CDF61C19F1; Fri, 17 Jan 2020 19:19:10 +0100 (CET) Date: Fri, 17 Jan 2020 18:19:10 -0000 From: "tip-bot2 for Pawan Gupta" Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/pti] x86/cpu: Update cached HLE state on write to TSX_CTRL_CPUID_CLEAR Cc: Pawan Gupta , Thomas Gleixner , Neelima Krishnan , Dave Hansen , Josh Poimboeuf , stable@vger.kernel.org, x86 , LKML In-Reply-To: =?utf-8?q?=3C2529b99546294c893dfa1c89e2b3e46da3369a59=2E1578?= =?utf-8?q?685425=2Egit=2Epawan=2Ekumar=2Egupta=40linux=2Eintel=2Ec?= =?utf-8?b?b20+?= References: =?utf-8?q?=3C2529b99546294c893dfa1c89e2b3e46da3369a59=2E15786?= =?utf-8?q?85425=2Egit=2Epawan=2Ekumar=2Egupta=40linux=2Eintel=2Eco?= =?utf-8?q?m=3E?= MIME-Version: 1.0 Message-ID: <157928515045.396.13108662649066370562.tip-bot2@tip-bot2> X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1, SHORTCIRCUIT=-0.0001 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org The following commit has been merged into the x86/pti branch of tip: Commit-ID: 5efc6fa9044c3356d6046c6e1da6d02572dbed6b Gitweb: https://git.kernel.org/tip/5efc6fa9044c3356d6046c6e1da6d02572dbed6b Author: Pawan Gupta AuthorDate: Fri, 10 Jan 2020 14:50:54 -08:00 Committer: Thomas Gleixner CommitterDate: Fri, 17 Jan 2020 19:13:46 +01:00 x86/cpu: Update cached HLE state on write to TSX_CTRL_CPUID_CLEAR /proc/cpuinfo currently reports Hardware Lock Elision (HLE) feature to be present on boot cpu even if it was disabled during the bootup. This is because cpuinfo_x86->x86_capability HLE bit is not updated after TSX state is changed via the new MSR IA32_TSX_CTRL. Update the cached HLE bit also since it is expected to change after an update to CPUID_CLEAR bit in MSR IA32_TSX_CTRL. Fixes: 95c5824f75f3 ("x86/cpu: Add a "tsx=" cmdline option with TSX disabled by default") Signed-off-by: Pawan Gupta Signed-off-by: Thomas Gleixner Tested-by: Neelima Krishnan Reviewed-by: Dave Hansen Reviewed-by: Josh Poimboeuf Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/2529b99546294c893dfa1c89e2b3e46da3369a59.1578685425.git.pawan.kumar.gupta@linux.intel.com --- arch/x86/kernel/cpu/tsx.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/tsx.c b/arch/x86/kernel/cpu/tsx.c index 3e20d32..032509a 100644 --- a/arch/x86/kernel/cpu/tsx.c +++ b/arch/x86/kernel/cpu/tsx.c @@ -115,11 +115,12 @@ void __init tsx_init(void) tsx_disable(); /* - * tsx_disable() will change the state of the - * RTM CPUID bit. Clear it here since it is now - * expected to be not set. + * tsx_disable() will change the state of the RTM and HLE CPUID + * bits. Clear them here since they are now expected to be not + * set. */ setup_clear_cpu_cap(X86_FEATURE_RTM); + setup_clear_cpu_cap(X86_FEATURE_HLE); } else if (tsx_ctrl_state == TSX_CTRL_ENABLE) { /* @@ -131,10 +132,10 @@ void __init tsx_init(void) tsx_enable(); /* - * tsx_enable() will change the state of the - * RTM CPUID bit. Force it here since it is now - * expected to be set. + * tsx_enable() will change the state of the RTM and HLE CPUID + * bits. Force them here since they are now expected to be set. */ setup_force_cpu_cap(X86_FEATURE_RTM); + setup_force_cpu_cap(X86_FEATURE_HLE); } }