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[209.85.220.65]) by mx.google.com with SMTPS id t7-v6sor4262804qkb.40.2018.10.15.08.32.39 for (Google Transport Security); Mon, 15 Oct 2018 08:32:39 -0700 (PDT) Received-SPF: pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M09IRZhO; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IK07FGdiT49t5RG4yYBjI5Av5y7V6yw5Er9ypNEcTYs=; b=M09IRZhOm4+Lf8/oNiVVvpTNUSuhgWskMBwLK7Ve+/ommLAzmQpLrSXJ0QS6Ga7fbQ dxvC0jVwJ1bsMRBOy1NITgH0HwEEWirMHczOKBB7WSVyGsIIeaFKYhxF5o5YzVu1Ixl6 jEmEoBgwF/rJ+wW1toiwfLOOXnOI3n1qVgESI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IK07FGdiT49t5RG4yYBjI5Av5y7V6yw5Er9ypNEcTYs=; b=k4VZS0RT4BhtoN8piT+FsJrEcmFSTFcIX9I0gq4IBLwug5SffHYGjFNHhU5ETiaLHo lurBCiJOBhUqI+JdyEMexO4hVWIJxoS6ILhW5A1QfVZ9QLxYpgj+muEyrMRT7P7/lOIX klo/+l/g8bbA09bQMyLFGJMJB/wtPju8TPWqrsbAcQMla5udRvvmu21j8wdXcavsKJYU IV9Ji6aYEdKgVDLk9IE6cKfGfa+Rnkg5VNj0sLQYd6LjfQtvXdgrjOIhofL4erVxy5uV dH4neG0Sa8nK6385c8xdzNDx1xIjuWRgmH5Ey0DFVd1/KkUmQ8Bp+kArGqnC2S8YHxHV igoQ== X-Gm-Message-State: ABuFfoiaTuTMlPJVPIAT8OTCYwrnrXWpWbAFzRP1IosOiFubzFwstQ+o pNOYkpodhIS2K9PXcMTgRMYLcq6E X-Google-Smtp-Source: ACcGV6103iVVV2eI4H/0tnuvYoPXykTvDdHd0DE8sepFlcvH39fdpPXsQuZ/n6yWHL7pp3vZTpl/xQ== X-Received: by 2002:a37:bc03:: with SMTP id m3-v6mr16472508qkf.114.1539617559385; Mon, 15 Oct 2018 08:32:39 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([72.71.243.63]) by smtp.googlemail.com with ESMTPSA id g82-v6sm10087768qkh.24.2018.10.15.08.32.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 15 Oct 2018 08:32:38 -0700 (PDT) From: David Long To: , Russell King - ARM Linux , Florian Fainelli , Tony Lindgren , Marc Zyngier , Mark Rutland Cc: Greg KH , Mark Brown Subject: [PATCH 4.14 17/24] ARM: spectre-v1: add array_index_mask_nospec() implementation Date: Mon, 15 Oct 2018 11:32:11 -0400 Message-Id: <1539617538-22328-18-git-send-email-dave.long@linaro.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1539617538-22328-1-git-send-email-dave.long@linaro.org> References: <1539617538-22328-1-git-send-email-dave.long@linaro.org> From: Russell King Commit 1d4238c56f9816ce0f9c8dbe42d7f2ad81cb6613 upstream. Add an implementation of the array_index_mask_nospec() function for mitigating Spectre variant 1 throughout the kernel. Signed-off-by: Russell King Acked-by: Mark Rutland Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Signed-off-by: David A. Long --- arch/arm/include/asm/barrier.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) -- 2.5.0 diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h index 3d9c1d4..69772e7 100644 --- a/arch/arm/include/asm/barrier.h +++ b/arch/arm/include/asm/barrier.h @@ -76,6 +76,25 @@ extern void arm_heavy_mb(void); #define __smp_rmb() __smp_mb() #define __smp_wmb() dmb(ishst) +#ifdef CONFIG_CPU_SPECTRE +static inline unsigned long array_index_mask_nospec(unsigned long idx, + unsigned long sz) +{ + unsigned long mask; + + asm volatile( + "cmp %1, %2\n" + " sbc %0, %1, %1\n" + CSDB + : "=r" (mask) + : "r" (idx), "Ir" (sz) + : "cc"); + + return mask; +} +#define array_index_mask_nospec array_index_mask_nospec +#endif + #include #endif /* !__ASSEMBLY__ */