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[209.85.220.65]) by mx.google.com with SMTPS id w7-v6sor12078029qvf.25.2018.10.15.08.32.38 for (Google Transport Security); Mon, 15 Oct 2018 08:32:38 -0700 (PDT) Received-SPF: pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M2y8u9x9; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=L+5yAe/iipO5lZy2PCQQfiQAFb3CHUNg0Jsea1KQFGM=; b=M2y8u9x9N6B1oXJDHgflyC1mK7EH5hJINXnHmWSVnHLXAQeJ8yhdaTSeBybG7FCzjA 5mtwZoydbfIVTIlgLeA3qWdR1HN1Tv8vbnEfJqWsZ8oyHTcYHAyP8SJ8H031gzR48yh4 XxwH+WH85xISVS+gvPnUACUmTJHzFrhErAct8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=L+5yAe/iipO5lZy2PCQQfiQAFb3CHUNg0Jsea1KQFGM=; b=suz+o+0PfncyB1p5dRvEowgViDj7MOumlU351kr668qgmjCGWT+iQrAcbYY7qZDYzz QEacIFjuhz3DE/hD11qlPnoj3LtK7f0+wdHc683+MzFiYpYnlXLeoqOebh8JqOJyeBXu nCIk4TbP5B0XqVoPlj0+QfRn45QfzKI2UCpBoW/tj5Wnh7iCEPzPd7PcoYg2o5rQxYMg hzOneJNGORJ+nqTw9z6FbTQnYa2qysGFOfOjq40OULxt+YGp9FqVf8IlIt4pxc1xZGUn fxJwm5HuFDCgtZZZhydpji2PYexmg57ddDt4DGWUru1CBa4ZXe5mhemolpcLwXVT/sSV N6Qw== X-Gm-Message-State: ABuFfogpavEPhn6EFsMbLePFkC+mf87t9EpMg64Ofk0Fr4Wme5gaP18Q W9HQxFsYKa2LC9DMfwyfvOZzPaYL X-Google-Smtp-Source: ACcGV6220DIQx+qgq57oilWBeR/+o27Cb/TKPxzqaib6NS6YBzAUHm36ELweQVyXXl1zyXvW9g+npA== X-Received: by 2002:a0c:98a6:: with SMTP id f35mr2359821qvd.224.1539617558140; Mon, 15 Oct 2018 08:32:38 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([72.71.243.63]) by smtp.googlemail.com with ESMTPSA id g82-v6sm10087768qkh.24.2018.10.15.08.32.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 15 Oct 2018 08:32:37 -0700 (PDT) From: David Long To: , Russell King - ARM Linux , Florian Fainelli , Tony Lindgren , Marc Zyngier , Mark Rutland Cc: Greg KH , Mark Brown Subject: [PATCH 4.14 16/24] ARM: spectre-v1: add speculation barrier (csdb) macros Date: Mon, 15 Oct 2018 11:32:10 -0400 Message-Id: <1539617538-22328-17-git-send-email-dave.long@linaro.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1539617538-22328-1-git-send-email-dave.long@linaro.org> References: <1539617538-22328-1-git-send-email-dave.long@linaro.org> From: Russell King Commit a78d156587931a2c3b354534aa772febf6c9e855 upstream. Add assembly and C macros for the new CSDB instruction. Signed-off-by: Russell King Acked-by: Mark Rutland Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Signed-off-by: David A. Long --- arch/arm/include/asm/assembler.h | 8 ++++++++ arch/arm/include/asm/barrier.h | 13 +++++++++++++ 2 files changed, 21 insertions(+) -- 2.5.0 diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 9342904..0cd4dcc 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -447,6 +447,14 @@ THUMB( orr \reg , \reg , #PSR_T_BIT ) .size \name , . - \name .endm + .macro csdb +#ifdef CONFIG_THUMB2_KERNEL + .inst.w 0xf3af8014 +#else + .inst 0xe320f014 +#endif + .endm + .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req #ifndef CONFIG_CPU_USE_DOMAINS adds \tmp, \addr, #\size - 1 diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h index 40f5c41..3d9c1d4 100644 --- a/arch/arm/include/asm/barrier.h +++ b/arch/arm/include/asm/barrier.h @@ -17,6 +17,12 @@ #define isb(option) __asm__ __volatile__ ("isb " #option : : : "memory") #define dsb(option) __asm__ __volatile__ ("dsb " #option : : : "memory") #define dmb(option) __asm__ __volatile__ ("dmb " #option : : : "memory") +#ifdef CONFIG_THUMB2_KERNEL +#define CSDB ".inst.w 0xf3af8014" +#else +#define CSDB ".inst 0xe320f014" +#endif +#define csdb() __asm__ __volatile__(CSDB : : : "memory") #elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6 #define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \ : : "r" (0) : "memory") @@ -37,6 +43,13 @@ #define dmb(x) __asm__ __volatile__ ("" : : : "memory") #endif +#ifndef CSDB +#define CSDB +#endif +#ifndef csdb +#define csdb() +#endif + #ifdef CONFIG_ARM_HEAVY_MB extern void (*soc_mb)(void); extern void arm_heavy_mb(void);