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[209.132.180.67]) by mx.google.com with ESMTP id i5si1736017pfb.330.2017.07.08.13.03.34; Sat, 08 Jul 2017 13:03:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=Z7TUyndm; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753115AbdGHUDe (ORCPT + 6 others); Sat, 8 Jul 2017 16:03:34 -0400 Received: from mail-pg0-f43.google.com ([74.125.83.43]:33113 "EHLO mail-pg0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753059AbdGHUDd (ORCPT ); Sat, 8 Jul 2017 16:03:33 -0400 Received: by mail-pg0-f43.google.com with SMTP id k14so31793458pgr.0 for ; Sat, 08 Jul 2017 13:03:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=D9mHJ7L0qSic+muxg79MyIIJ88dQsuT6UlmlH0B0rCs=; b=Z7TUyndmd7mtbVc8AdDamHsYUi50KUfQYi3PG0HBQhBSpWn6abg+PhWK+Bsfmg3Us2 YFUlISF1FfXCCmSJPq1LcIuBa5iWyFNHIXIhPKX01oSId6YNQxGygJrJHpnMmj+GI5s0 YloYJ06C4o5/9mWG7w52r9QFPi3m26kHywVVY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=D9mHJ7L0qSic+muxg79MyIIJ88dQsuT6UlmlH0B0rCs=; b=LE2c4F0iFLbBNV2kODBJreaEYvipl1woXNB3MiSMSyvkRNjFEaUcgr+vK9R7uHnMLn s+F3QXgqZnpbyrlY9Tzy6W5t0NpjI6K4sRUTpT035o5s7cg3AZEsQsTYWQyLzMZGlaij eVYEw2pL6PcBStiRiZuuqIw4X7lnSMS8dUsE41xzZTH4OunRrwDH4ZkX0/xPs3DfGgC7 KBdQw1guLfURD7uYTPiq2+tqVl6gC7fOO0BMjOtZWHnkyAeGilA9Kzdn+CaUd0uHBSIt B5doxMIauvkv2jbkWGybbspXnP6O6rmEeftxnVnTOYDnx3OfRxZmamnKoSvUEqALhNzl Ylcg== X-Gm-Message-State: AIVw1108KTRsb+UTd7h2THo8JyvN0v5urPc9OaVG1iw49yHHSdIsLqAN 4bEgJvjDu7FeqVMmVPP1nQ== X-Received: by 10.84.254.11 with SMTP id b11mr9748317plm.250.1499544212794; Sat, 08 Jul 2017 13:03:32 -0700 (PDT) Received: from localhost.localdomain ([106.51.234.165]) by smtp.gmail.com with ESMTPSA id m79sm1155703pfk.35.2017.07.08.13.03.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 08 Jul 2017 13:03:31 -0700 (PDT) From: Amit Pundir To: Greg KH , Eric Anholt Cc: Stable Subject: [PATCH for-4.4.y 2/5] drm/vc4: Initialize scaler DISPBKGND on modeset. Date: Sun, 9 Jul 2017 01:33:18 +0530 Message-Id: <1499544201-12812-3-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1499544201-12812-1-git-send-email-amit.pundir@linaro.org> References: <1499544201-12812-1-git-send-email-amit.pundir@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Eric Anholt commit 6a609209865247cc748e90158c99f374f79b494c upstream. We weren't updating the interlaced bit, so we'd scan out incorrectly if the firmware had brought up the TV encoder and we were switching to HDMI. Signed-off-by: Eric Anholt Signed-off-by: Amit Pundir --- drivers/gpu/drm/vc4/vc4_crtc.c | 6 ++++++ drivers/gpu/drm/vc4/vc4_regs.h | 14 ++++++++++++++ 2 files changed, 20 insertions(+) -- 2.13.0 diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index 265064c62d49..784a450d3e72 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -182,6 +182,8 @@ static int vc4_get_clock_select(struct drm_crtc *crtc) static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) { + struct drm_device *dev = crtc->dev; + struct vc4_dev *vc4 = to_vc4_dev(dev); struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); struct drm_crtc_state *state = crtc->state; struct drm_display_mode *mode = &state->adjusted_mode; @@ -240,6 +242,10 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) PV_CONTROL_FIFO_CLR | PV_CONTROL_EN); + HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel), + SCALER_DISPBKGND_AUTOHS | + (interlace ? SCALER_DISPBKGND_INTERLACE : 0)); + if (debug_dump_regs) { DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc)); vc4_crtc_dump_regs(vc4_crtc); diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h index 9e4e904c668e..06f5d298a651 100644 --- a/drivers/gpu/drm/vc4/vc4_regs.h +++ b/drivers/gpu/drm/vc4/vc4_regs.h @@ -350,6 +350,17 @@ # define SCALER_DISPCTRLX_HEIGHT_SHIFT 0 #define SCALER_DISPBKGND0 0x00000044 +# define SCALER_DISPBKGND_AUTOHS BIT(31) +# define SCALER_DISPBKGND_INTERLACE BIT(30) +# define SCALER_DISPBKGND_GAMMA BIT(29) +# define SCALER_DISPBKGND_TESTMODE_MASK VC4_MASK(28, 25) +# define SCALER_DISPBKGND_TESTMODE_SHIFT 25 +/* Enables filling the scaler line with the RGB value in the low 24 + * bits before compositing. Costs cycles, so should be skipped if + * opaque display planes will cover everything. + */ +# define SCALER_DISPBKGND_FILL BIT(24) + #define SCALER_DISPSTAT0 0x00000048 #define SCALER_DISPBASE0 0x0000004c # define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30) @@ -362,6 +373,9 @@ # define SCALER_DISPSTATX_EMPTY BIT(28) #define SCALER_DISPCTRL1 0x00000050 #define SCALER_DISPBKGND1 0x00000054 +#define SCALER_DISPBKGNDX(x) (SCALER_DISPBKGND0 + \ + (x) * (SCALER_DISPBKGND1 - \ + SCALER_DISPBKGND0)) #define SCALER_DISPSTAT1 0x00000058 #define SCALER_DISPSTATX(x) (SCALER_DISPSTAT0 + \ (x) * (SCALER_DISPSTAT1 - \