From patchwork Thu Apr 6 12:49:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Pundir X-Patchwork-Id: 96952 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp714313qgd; Thu, 6 Apr 2017 05:49:45 -0700 (PDT) X-Received: by 10.98.32.10 with SMTP id g10mr35217952pfg.37.1491482985547; Thu, 06 Apr 2017 05:49:45 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s4si1781387pgc.281.2017.04.06.05.49.45; Thu, 06 Apr 2017 05:49:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757215AbdDFMtm (ORCPT + 6 others); Thu, 6 Apr 2017 08:49:42 -0400 Received: from mail-pg0-f46.google.com ([74.125.83.46]:35085 "EHLO mail-pg0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757177AbdDFMtf (ORCPT ); Thu, 6 Apr 2017 08:49:35 -0400 Received: by mail-pg0-f46.google.com with SMTP id 81so35574200pgh.2 for ; Thu, 06 Apr 2017 05:49:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SgcbcNIVf6PVs7VkdNYhv13Y71rJlBahQc+9Wap4k2A=; b=j7hQQXh0NBncW3bfJ1d7vjzathp91X6bwwDEWIlCSDVH+QyWXQBPkDYmxdP6F3qWaH 8g77lZS4f0dVofToMTSxXdP49wy8gesHD5NxVAko/Ov4vNE+OupPqBokidjqJtqf7hRS DBCg3rMuPf9LZQBpseA+2BjqlezKZZ6Ve/KHc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SgcbcNIVf6PVs7VkdNYhv13Y71rJlBahQc+9Wap4k2A=; b=lPYo2yMksIe/xXKh48iSthflmlB7OMXJIyEvbU2tIpGEvG/+/1x3+vPVBdf2S0bBt3 yTc71oPRNKnMna8mv/dgeLOiQSKWJV0InLU2W1CmvOk1buQTBJpU0w2l/SKU4heuzfxV lAsYpiwXt5knjZop0k5miojXqyTrcdtO/h98S2zyg14Igy/YIO9a3xBplZM/kmDybMMK Sc1AfPRyNjxdIz3FORQ8kZo3AVd85F06C/9oiEJD6nHuniZUu2tWlpes2393J98zCEWy yD4+O/DThUpCpYzFegEGsgIECY9LtiwCuPmNsqkAKfVZ6HHjbCTyqdCjT98M/T8+EkXl 54UQ== X-Gm-Message-State: AFeK/H3Nemk94560KFX87DT51CNk6q2o37FLEQfFWvzn06xBANNZdU4vHaQ4SXE09fBP+cSe X-Received: by 10.98.71.149 with SMTP id p21mr35780219pfi.94.1491482969863; Thu, 06 Apr 2017 05:49:29 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id n7sm3892564pfn.0.2017.04.06.05.49.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 06 Apr 2017 05:49:29 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, james.hogan@imgtec.com, Felix Fietkau , linux-mips@linux-mips.org Subject: [PATCH for-4.4 7/7] MIPS: Lantiq: Fix cascaded IRQ setup Date: Thu, 6 Apr 2017 18:19:00 +0530 Message-Id: <1491482940-1163-8-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491482940-1163-1-git-send-email-amit.pundir@linaro.org> References: <1491482940-1163-1-git-send-email-amit.pundir@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Felix Fietkau With the IRQ stack changes integrated, the XRX200 devices started emitting a constant stream of kernel messages like this: [ 565.415310] Spurious IRQ: CAUSE=0x1100c300 This is caused by IP0 getting handled by plat_irq_dispatch() rather than its vectored interrupt handler, which is fixed by commit de856416e714 ("MIPS: IRQ Stack: Fix erroneous jal to plat_irq_dispatch"). Fix plat_irq_dispatch() to handle non-vectored IPI interrupts correctly by setting up IP2-6 as proper chained IRQ handlers and calling do_IRQ for all MIPS CPU interrupts. Signed-off-by: Felix Fietkau Acked-by: John Crispin Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/15077/ [james.hogan@imgtec.com: tweaked commit message] Signed-off-by: James Hogan (cherry picked from commit 6c356eda225e3ee134ed4176b9ae3a76f793f4dd) Signed-off-by: Amit Pundir --- arch/mips/lantiq/irq.c | 38 +++++++++++++++++--------------------- 1 file changed, 17 insertions(+), 21 deletions(-) -- 2.7.4 diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index 2e7f60c..51cdc46 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -269,6 +269,11 @@ static void ltq_hw5_irqdispatch(void) DEFINE_HWx_IRQDISPATCH(5) #endif +static void ltq_hw_irq_handler(struct irq_desc *desc) +{ + ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2); +} + #ifdef CONFIG_MIPS_MT_SMP void __init arch_init_ipiirq(int irq, struct irqaction *action) { @@ -313,23 +318,19 @@ static struct irqaction irq_call = { asmlinkage void plat_irq_dispatch(void) { unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; - unsigned int i; - - if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) { - do_IRQ(MIPS_CPU_TIMER_IRQ); - goto out; - } else { - for (i = 0; i < MAX_IM; i++) { - if (pending & (CAUSEF_IP2 << i)) { - ltq_hw_irqdispatch(i); - goto out; - } - } + int irq; + + if (!pending) { + spurious_interrupt(); + return; } - pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status()); -out: - return; + pending >>= CAUSEB_IP; + while (pending) { + irq = fls(pending) - 1; + do_IRQ(MIPS_CPU_IRQ_BASE + irq); + pending &= ~BIT(irq); + } } static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) @@ -354,11 +355,6 @@ static const struct irq_domain_ops irq_domain_ops = { .map = icu_map, }; -static struct irqaction cascade = { - .handler = no_action, - .name = "cascade", -}; - int __init icu_of_init(struct device_node *node, struct device_node *parent) { struct device_node *eiu_node; @@ -390,7 +386,7 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent) mips_cpu_irq_init(); for (i = 0; i < MAX_IM; i++) - setup_irq(i + 2, &cascade); + irq_set_chained_handler(i + 2, ltq_hw_irq_handler); if (cpu_has_vint) { pr_info("Setting up vectored interrupts\n");