From patchwork Tue Apr 4 06:17:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Pundir X-Patchwork-Id: 96673 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp48108qgd; Mon, 3 Apr 2017 23:17:41 -0700 (PDT) X-Received: by 10.84.224.131 with SMTP id s3mr26740204plj.162.1491286661835; Mon, 03 Apr 2017 23:17:41 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a9si746909pgf.57.2017.04.03.23.17.41; Mon, 03 Apr 2017 23:17:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750961AbdDDGRl (ORCPT + 6 others); Tue, 4 Apr 2017 02:17:41 -0400 Received: from mail-pg0-f44.google.com ([74.125.83.44]:34549 "EHLO mail-pg0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751066AbdDDGRk (ORCPT ); Tue, 4 Apr 2017 02:17:40 -0400 Received: by mail-pg0-f44.google.com with SMTP id 21so142750424pgg.1 for ; Mon, 03 Apr 2017 23:17:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Y8zOukan2JejQjnNm7LJz+LbfC8C/DLn0s86i/CVMzM=; b=ZBaPkuwkhM5CPqUIovzf5SP7w3Z30JdPFP00pGmyWlWraPQ+jbXu55PU5r6Baxg5dB 6Vh2uRy9JLhln70mCbzmUhL5tNgJMqekXQhenMO/mDU89ll5duCDnFscJlUGyc7pxRuV j7tVKFVkaXuWIztfHUjSutSvFap0xXu4e3e7s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Y8zOukan2JejQjnNm7LJz+LbfC8C/DLn0s86i/CVMzM=; b=e/rFWGLFK2nStei8Gd0wA4A4/j+d09IZH47AjMAaWyAUdUG167nFQiP8hXiiFQdpmk sWSji0JgWy/d0BwWcVekv7S2ADRNvNHsWU8mR+p1Z7rTsUYmg4dyZZ6yrVDTw/zPy1I2 SwqieTiVA7OuSdn/+efQyvvK13FOPNg3VAdYbabB2tGW9k5VND3VrCW4x5rLYJ/2c+xR q48HWsdH20ZhwzyNYaHPJMyuHhzcpVYjrcX6h5IB9lpXBQ/kchsUIPnV0d0VRJwV2fji tL4CfbznH4Q6AqdFp0KEbIYoZH98CtPyizqUE/ZYm7XBQ2GaIWUAoh4llOxeTT4T43C1 FHvg== X-Gm-Message-State: AFeK/H1JDIh+Bbr5P6aFcTYqt97PAaFb1abiil514NwcVYhZeY81zfQfdVXtNXS4SH3HKB2w X-Received: by 10.98.36.81 with SMTP id r78mr21350673pfj.178.1491286659952; Mon, 03 Apr 2017 23:17:39 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id l126sm29224804pfl.56.2017.04.03.23.17.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 03 Apr 2017 23:17:39 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, Boris Brezillon , Stephen Boyd Subject: [PATCH 11/33] clk: bcm: Allow rate change propagation to PLLH_AUX on VEC clock Date: Tue, 4 Apr 2017 11:47:25 +0530 Message-Id: <1491286653-31193-2-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491286653-31193-1-git-send-email-amit.pundir@linaro.org> References: <1491286653-31193-1-git-send-email-amit.pundir@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Boris Brezillon The VEC clock requires needs to be set at exactly 108MHz. Allow rate change propagation on PLLH_AUX to match this requirement wihtout impacting other IPs (PLLH is currently only used by the HDMI encoder, which cannot be enabled when the VEC encoder is enabled). Signed-off-by: Boris Brezillon Reviewed-by: Eric Anholt Signed-off-by: Stephen Boyd (cherry picked from commit d86d46af84855403c00018be1c3e7bc190f2a6cd) Signed-off-by: Amit Pundir --- drivers/clk/bcm/clk-bcm2835.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index df96fe6..eaf82f4 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -1861,7 +1861,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .ctl_reg = CM_VECCTL, .div_reg = CM_VECDIV, .int_bits = 4, - .frac_bits = 0), + .frac_bits = 0, + /* + * Allow rate change propagation only on PLLH_AUX which is + * assigned index 7 in the parent array. + */ + .set_rate_parent = BIT(7)), /* dsi clocks */ [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(