From patchwork Mon Nov 3 18:46:39 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 40076 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ee0-f71.google.com (mail-ee0-f71.google.com [74.125.83.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id B65BC21894 for ; Mon, 3 Nov 2014 18:47:27 +0000 (UTC) Received: by mail-ee0-f71.google.com with SMTP id e51sf3207181eek.10 for ; Mon, 03 Nov 2014 10:47:26 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:mime-version:in-reply-to:references :date:message-id:from:to:cc:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list:content-type; bh=RTzKy1BwqdA8kIWgKlby8zmLZsUNWOAPu7wqN/QvXrw=; b=bRGA+a5sUvJwSBP8v81hgENzu9cglc34IjWvU/MELxR+jrpmbl3zLZIDgXjm7i+n1t +D+JeCv2A0zWNmzDJrHCoNUCXfUC3h8QutCWTieoSi8bgY5QFaHeO3tu17yyO7pKI07f 4c6dBXEZupWcyZdXenx0yd8oibHdERsBh2+WyX/hF4dYJwvCV2soO+Qf7m/5VrlqWGys 7jP5NXDnuwH43xtW+dP3pajgvWvAG0L5+nELB8jcnspQ3h28NoOGbIAFMpT0japRjYtZ 6RWhzIjB961bcVp5Jqh+PnfkmgvFjBwvWgygJVTwl2van5U55N0kfLSn9u2715SX8CzU rTSA== X-Gm-Message-State: ALoCoQmd3p8kP0nJipDZvZUoVay35sVV0ZGUZb3325yEk8IgeWo+0qXik8Wr8VxRT3iWCj7wmbGg X-Received: by 10.112.55.10 with SMTP id n10mr755474lbp.14.1415040446820; Mon, 03 Nov 2014 10:47:26 -0800 (PST) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.120.169 with SMTP id ld9ls799716lab.12.gmail; Mon, 03 Nov 2014 10:47:26 -0800 (PST) X-Received: by 10.152.26.226 with SMTP id o2mr46017351lag.50.1415040446643; Mon, 03 Nov 2014 10:47:26 -0800 (PST) Received: from mail-lb0-f171.google.com (mail-lb0-f171.google.com. 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id k45si8591890qgd.92.2014.11.03.10.47.24 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 03 Nov 2014 10:47:25 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:36785 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlMey-0002ti-9S for patch@linaro.org; Mon, 03 Nov 2014 13:47:24 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55779) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlMeM-0002Lk-DO for qemu-devel@nongnu.org; Mon, 03 Nov 2014 13:46:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XlMeH-00088e-Uw for qemu-devel@nongnu.org; Mon, 03 Nov 2014 13:46:46 -0500 Received: from mail-qa0-f47.google.com ([209.85.216.47]:53653) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlMeH-00088a-Pz for qemu-devel@nongnu.org; Mon, 03 Nov 2014 13:46:41 -0500 Received: by mail-qa0-f47.google.com with SMTP id dc16so8688001qab.6 for ; Mon, 03 Nov 2014 10:46:39 -0800 (PST) MIME-Version: 1.0 X-Received: by 10.224.86.68 with SMTP id r4mr68861510qal.55.1415040399219; Mon, 03 Nov 2014 10:46:39 -0800 (PST) Received: by 10.96.136.168 with HTTP; Mon, 3 Nov 2014 10:46:39 -0800 (PST) In-Reply-To: <2195206.F4HeItVKYs@dabox> References: <1533701.HoIoT00ynE@dabox> <2195206.F4HeItVKYs@dabox> Date: Mon, 3 Nov 2014 12:46:39 -0600 Message-ID: From: Greg Bellows To: Tim Sander X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.216.47 Cc: QEMU Developers Subject: Re: [Qemu-devel] State of ARM FIQ in Qemu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.171 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 On 3 November 2014 10:22, Tim Sander wrote: > Hi Greg > > Thanks for your fast reply. > > I am still in the process of getting the security extension portion of > the > > GIC patches fully up and running. By the sounds of your use, it sounds > > like you just want FIQ support not necessarily secure GIC support. Would > > this be correct? > Yes. More elaborate i am working on a modified cortexa9 versatile express, > where i added my virtual test hardware. > > > I recently sent out an updated set of patches for review that contain GIC > > interrupt grouping and FIQ enablement along with secure extension > > infrastructure. If interested, you can find the patches here: > > > > http://lists.nongnu.org/archive/html/qemu-devel/2014-10/msg03921.html > > > > Alternatively, it sounds like you have access to the Linaro GIT repos, in > > which case you can use the following repo/branch that contains the same > > patches. It is based on fairly recent upstream bits. > > > > repo: git://git.linaro.org/people/greg.bellows/qemu.git > > branch: tzqemu_gic_v2 > > > > If you don't need the security extensions, then you shouldn't need to do > > anything to the code to get FIQ support on vexpress-a9/15 or virt > machines. > Ok but i think i see a RAZ codepath in qemu when accessing the gic > registers > configuring the interrupt group. > > Please let me know if you have any further questions or issues. > I have the problem that the secure_extn property is not set and i have not > figured out a way to set these. The corresponding code is a slighly > modified > vexpress_common_init in hw/arm/vexpress.c.:519. > > I guess setting the property would be done by > qdev_prop_set_bool(dev,"security_extn",TRUE); > but i fail to find the "dev" from the GIC i could use as argument. > > Attached is also a snipped from a debugger run verifing that its indeed > s->security-extn which is missing. > > Ah... Yes, using A9 (GICv1) which means you don't have grouping without the security extensions. I tried enabling the security extensions and things hung, however, I was able to boot A9 Linux and use FIQs with the following change: diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index c09358c..813ae92 100644 This may be at least a workaround for you while I figure out where the security configuration gets hung-up. Can you give this a try and see if you can make progress? The security extensions aspect of the code is fairly untested as I still need secure address space support, so there may be glitches when security is enabled. Best regards > Tim > > Breakpoint 3, gic_dist_writeb (opaque=0x555556368a80, offset=136, value=0) > at > hw/intc/arm_gic.c:820 > 820 } else if (offset >= 0x80) { > (gdb) list > 815 s->enabled = (value & 0x1); > 816 DPRINTF("Distribution %sabled\n", s->enabled ? > "En" : > "Dis"); > 817 } > 818 } else if (offset < 4) { > 819 /* ignored. */ > 820 } else if (offset >= 0x80) { > 821 /* Interrupt Group Registers > 822 * > 823 * For GIC with Security Extn and Non-secure access > RAZ/WI > 824 * For GICv1 without Security Extn RAZ/WI > (gdb) n > 826 if (!(s->security_extn && ns_access()) && > (gdb) n > 828 || s->revision == 2)) { > (gdb) n > 999 gic_update(s); > (gdb) print s->security_extn > $2 = false > > --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -29,6 +29,8 @@ static void a9mp_priv_initfn(Object *obj) object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC); qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); + qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); object_initialize(&s->gtimer, sizeof(s->gtimer), TYPE_A9_GTIMER); qdev_set_parent_bus(DEVICE(&s->gtimer), sysbus_get_default());