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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id e15si1027820qac.30.2014.09.26.02.11.55 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 26 Sep 2014 02:11:55 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:46136 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XXRZC-0006cn-S1 for patch@linaro.org; Fri, 26 Sep 2014 05:11:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52556) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XXRYU-0005wP-83 for qemu-devel@nongnu.org; Fri, 26 Sep 2014 05:11:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XXRYP-0003QP-Dy for qemu-devel@nongnu.org; Fri, 26 Sep 2014 05:11:10 -0400 Received: from mail-pd0-f176.google.com ([209.85.192.176]:49653) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XXRYP-0003Pv-8H for qemu-devel@nongnu.org; Fri, 26 Sep 2014 05:11:05 -0400 Received: by mail-pd0-f176.google.com with SMTP id z10so11068109pdj.35 for ; Fri, 26 Sep 2014 02:10:59 -0700 (PDT) X-Received: by 10.68.228.37 with SMTP id sf5mr29324137pbc.154.1411722659593; Fri, 26 Sep 2014 02:10:59 -0700 (PDT) MIME-Version: 1.0 Received: by 10.70.133.136 with HTTP; Fri, 26 Sep 2014 02:10:38 -0700 (PDT) In-Reply-To: <1410332571-10544-6-git-send-email-ard.biesheuvel@linaro.org> References: <1410332571-10544-1-git-send-email-ard.biesheuvel@linaro.org> <1410332571-10544-6-git-send-email-ard.biesheuvel@linaro.org> From: Peter Maydell Date: Fri, 26 Sep 2014 10:10:38 +0100 Message-ID: To: Ard Biesheuvel X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.176 Cc: Rob Herring , QEMU Developers , Christoffer Dall Subject: Re: [Qemu-devel] [PACTH v4 5/6] target-arm: add emulation of PSCI calls for system emulation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 On 10 September 2014 08:02, Ard Biesheuvel wrote: > From: Rob Herring > > Add support for handling PSCI calls in system emulation. Both version > 0.1 and 0.2 of the PSCI spec are supported. Platforms can enable support > by setting the "psci-conduit" QOM property on the cpus to SMC or HVC > emulation and having a PSCI binding in their dtb. > > Signed-off-by: Rob Herring > Signed-off-by: Ard Biesheuvel > + case QEMU_PSCI_0_2_FN_SYSTEM_RESET: > + qemu_system_reset_request(); > + break; > + case QEMU_PSCI_0_2_FN_SYSTEM_OFF: > + qemu_system_shutdown_request(); > + break; I just realised that this isn't quite right: PSCI mandates that the SYSTEM_RESET and SYSTEM_OFF functions never return to the caller, but the QEMU qemu_system_*_request() functions are just requests which the main loop will later handle asynchronously. So we should put the calling CPU into power off (and rely on CPU reset to power it up again if it's CPU 0; we don't care if we're shutting down, obviously). I propose to apply the following fixup patch to deal with this (since this patchset is very nearly ready and I know Ard's not going to be back to deal with it for a few weeks): thanks -- PMM diff --git a/target-arm/psci.c b/target-arm/psci.c index 7347cbd..1cda7d3 100644 --- a/target-arm/psci.c +++ b/target-arm/psci.c @@ -85,10 +85,15 @@ bool arm_handle_psci(CPUState *cs) break; case QEMU_PSCI_0_2_FN_SYSTEM_RESET: qemu_system_reset_request(); - break; + /* QEMU reset and shutdown are async requests, but PSCI + * mandates that we never return from the reset/shutdown + * call, so power the CPU off now so it doesn't execute + * anything further. + */ + goto cpu_off; case QEMU_PSCI_0_2_FN_SYSTEM_OFF: qemu_system_shutdown_request(); - break; + goto cpu_off; case QEMU_PSCI_0_1_FN_CPU_ON: case QEMU_PSCI_0_2_FN_CPU_ON: case QEMU_PSCI_0_2_FN64_CPU_ON: @@ -144,11 +149,7 @@ bool arm_handle_psci(CPUState *cs) break; case QEMU_PSCI_0_1_FN_CPU_OFF: case QEMU_PSCI_0_2_FN_CPU_OFF: - cpu->powered_off = true; - cs->halted = 1; - cs->exception_index = EXCP_HLT; - cpu_loop_exit(cs); - /* notreached */ + goto cpu_off; case QEMU_PSCI_0_1_FN_CPU_SUSPEND: case QEMU_PSCI_0_2_FN_CPU_SUSPEND: case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: @@ -180,4 +181,11 @@ err: env->regs[0] = ret; } return true; + +cpu_off: + cpu->powered_off = true; + cs->halted = 1; + cs->exception_index = EXCP_HLT; + cpu_loop_exit(cs); + /* notreached */ }