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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id q78si11126775qgq.84.2015.05.18.11.42.23 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 18 May 2015 11:42:24 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:42508 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YuPzb-00081y-8J for patch@linaro.org; Mon, 18 May 2015 14:42:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60650) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YuPz9-0007kh-E0 for qemu-devel@nongnu.org; Mon, 18 May 2015 14:41:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YuPz4-0003DN-9w for qemu-devel@nongnu.org; Mon, 18 May 2015 14:41:55 -0400 Received: from mail-ie0-f180.google.com ([209.85.223.180]:32810) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YuPz4-0003DB-5M for qemu-devel@nongnu.org; Mon, 18 May 2015 14:41:50 -0400 Received: by iebgx4 with SMTP id gx4so178070015ieb.0 for ; Mon, 18 May 2015 11:41:49 -0700 (PDT) X-Received: by 10.107.131.157 with SMTP id n29mr6471164ioi.74.1431974509467; Mon, 18 May 2015 11:41:49 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.181.6 with HTTP; Mon, 18 May 2015 11:41:29 -0700 (PDT) In-Reply-To: <1431499963-1019-5-git-send-email-edgar.iglesias@gmail.com> References: <1431499963-1019-1-git-send-email-edgar.iglesias@gmail.com> <1431499963-1019-5-git-send-email-edgar.iglesias@gmail.com> From: Peter Maydell Date: Mon, 18 May 2015 19:41:29 +0100 Message-ID: To: "Edgar E. Iglesias" X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.223.180 Cc: Edgar Iglesias , Alexander Graf , QEMU Developers , Greg Bellows , Sergey Fedorov , =?UTF-8?B?QWxleCBCZW5uw6ll?= Subject: Re: [Qemu-devel] [PATCH v1 04/18] target-arm: Route timer access traps to EL1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.44 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 On 13 May 2015 at 07:52, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Signed-off-by: Edgar E. Iglesias > --- > target-arm/helper.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index a4bab78..d849b30 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -1147,6 +1147,7 @@ static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri) > { > /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */ > if (arm_current_el(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) { > + env->exception.target_el = 1; > return CP_ACCESS_TRAP; > } > return CP_ACCESS_OK; > @@ -1157,6 +1158,7 @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx) > /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */ > if (arm_current_el(env) == 0 && > !extract32(env->cp15.c14_cntkctl, timeridx, 1)) { > + env->exception.target_el = 1; > return CP_ACCESS_TRAP; > } > return CP_ACCESS_OK; > @@ -1169,6 +1171,7 @@ static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx) > */ > if (arm_current_el(env) == 0 && > !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { > + env->exception.target_el = 1; > return CP_ACCESS_TRAP; > } > return CP_ACCESS_OK; If EL3 is 32-bit and we're in Secure EL0 then the correct target_el is 3, not 1, so what you actually want here is exception_target_el(). More generally, this seems to be a really easy mistake to make with access functions. At the moment we come pretty close to being able to say "always set both exception.target_el and exception.syndrome in the same place in the code". So I think the correct fix is g_assert_not_reached(); in the "Extend helpers to route exceptions" patch. If we get any registers where the correct target EL is something other than that, we should have new CP_ACCESS_* enums for them. Then the only place where we don't set both syndrome and target_el at the same time are: * msr_i_pstate is failing to set a syndrome * arm_debug_excp_handler() needs to set the target_el to the debug target el * arm_cpu_handle_mmu_fault should set the target_el * the FIQ/IRQ/VIRQ/VFIQ paths in arm_cpu_exec_interrupt don't set syndrome, because they're interrupts and there's no syndrome info Note that the first three of these are all bugs, which is a nice demonstration of the utility of the rule. I think I'd also like to make the FIQ&c code set exception.syndrome to an invalid value, because then we can probably write some assertions for exception entry (and also because then we're consistent about things.) That seems like more than I really feel I can justify just fixing in target-arm.next, so I think I'll drop Greg's patches 1..3 from target-arm.next and send them out as part of a series which does the above changes. thanks -- PMM --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -333,9 +333,11 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome) return; case CP_ACCESS_TRAP: env->exception.syndrome = syndrome; + env->target_el = exception_target_el(env); break; case CP_ACCESS_TRAP_UNCATEGORIZED: env->exception.syndrome = syn_uncategorized(); + env->target_el = exception_target_el(env); break; default: