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[209.85.216.45]) by mx.google.com with ESMTPS id cr7si9172418vdd.95.2015.07.24.03.06.20 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Jul 2015 03:06:21 -0700 (PDT) Received-SPF: pass (google.com: domain of peter.maydell@linaro.org designates 209.85.216.45 as permitted sender) client-ip=209.85.216.45; Received: by vnds125 with SMTP id s125so7172379vnd.1 for ; Fri, 24 Jul 2015 03:06:20 -0700 (PDT) X-Received: by 10.52.2.170 with SMTP id 10mr16003777vdv.93.1437732380706; Fri, 24 Jul 2015 03:06:20 -0700 (PDT) MIME-Version: 1.0 Received: by 10.31.153.135 with HTTP; Fri, 24 Jul 2015 03:06:01 -0700 (PDT) In-Reply-To: <20150724094802.GA22633@toto> References: <1437047249-2357-1-git-send-email-peter.maydell@linaro.org> <1437047249-2357-2-git-send-email-peter.maydell@linaro.org> <20150724094802.GA22633@toto> From: Peter Maydell Date: Fri, 24 Jul 2015 11:06:01 +0100 Message-ID: Subject: Re: [PATCH 1/4] target-arm: Add the AArch64 view of the Secure physical timer To: "Edgar E. Iglesias" Cc: QEMU Developers , Patch Tracking X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.54 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , On 24 July 2015 at 10:48, Edgar E. Iglesias wrote: > On Thu, Jul 16, 2015 at 12:47:26PM +0100, Peter Maydell wrote: >> + { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64, >> + .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2, >> + .type = ARM_CP_IO, >> + .accessfn = gt_stimer_access, >> + .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), >> + .writefn = gt_sec_cval_write, .raw_writefn = raw_write, > I think you've missed a .access = PL1_RW here. With that change the series passes my sectimer tests. Yep, you're right, this needs to be folded into this patch: (I won't bother resending unless there are other fixes that need to be made too.) thanks -- PMM --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1679,7 +1679,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { }, { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2, - .type = ARM_CP_IO, + .type = ARM_CP_IO, .access = PL1_RW, .accessfn = gt_stimer_access, .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), .writefn = gt_sec_cval_write, .raw_writefn = raw_write,