| Message ID | 6adfabd1e61f13932b99d7a9f6839a5c87ad8ce7.1603467169.git.alistair.francis@wdc.com |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V: Start to remove xlen preprocess | expand |
On Fri, Oct 23, 2020 at 11:45 PM Alistair Francis <alistair.francis@wdc.com> wrote: > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/cpu.h | 2 ++ > target/riscv/cpu.c | 9 +++++++++ > 2 files changed, 11 insertions(+) > Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 74a236d4bc..86b063543d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -383,6 +383,8 @@ FIELD(TB_FLAGS, LMUL, 3, 2) FIELD(TB_FLAGS, SEW, 5, 3) FIELD(TB_FLAGS, VILL, 8, 1) +bool riscv_cpu_is_32bit(CPURISCVState *env); + /* * A simplification for VLMAX * = (1 << LMUL) * VLEN / (8 * (1 << SEW)) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0bbfd7f457..32234d4a70 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -107,6 +107,15 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) } } +bool riscv_cpu_is_32bit(CPURISCVState *env) +{ + if (env->misa & RV64) { + return false; + } + + return true; +} + static void set_misa(CPURISCVState *env, target_ulong misa) { env->misa_mask = env->misa = misa;
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/cpu.h | 2 ++ target/riscv/cpu.c | 9 +++++++++ 2 files changed, 11 insertions(+)