diff mbox series

[v1,11/16] target/riscv: cpu: Remove compile time XLEN checks

Message ID 594ed654cb36645d4c1b0aa3596f3e70d2ec5f7f.1603467169.git.alistair.francis@wdc.com
State New
Headers show
Series RISC-V: Start to remove xlen preprocess | expand

Commit Message

Alistair Francis Oct. 23, 2020, 3:33 p.m. UTC 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h |  6 ++----
 target/riscv/cpu.c | 17 +++++++++--------
 2 files changed, 11 insertions(+), 12 deletions(-)

Comments

Bin Meng Oct. 26, 2020, 8:56 a.m. UTC | #1 
On Fri, Oct 23, 2020 at 11:45 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/cpu.h |  6 ++----
>  target/riscv/cpu.c | 17 +++++++++--------
>  2 files changed, 11 insertions(+), 12 deletions(-)
>

Reviewed-by: Bin Meng <bin.meng@windriver.com>
diff mbox series

Patch

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 86b063543d..6096243aed 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -151,13 +151,11 @@  struct CPURISCVState {
 
     target_ulong mhartid;
     target_ulong mstatus;
+    /* This is RV32 only */
+    target_ulong mstatush;
 
     target_ulong mip;
 
-#ifdef TARGET_RISCV32
-    target_ulong mstatush;
-#endif
-
     uint32_t miclaim;
 
     target_ulong mie;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8f8c568974..1b3efc1c81 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -239,9 +239,9 @@  static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 #ifndef CONFIG_USER_ONLY
     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
-#ifdef TARGET_RISCV32
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", env->mstatush);
-#endif
+    if (riscv_cpu_is_32bit(env)) {
+        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", env->mstatush);
+    }
     if (riscv_has_ext(env, RVH)) {
         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", env->vsstatus);
@@ -353,11 +353,12 @@  static void riscv_cpu_reset(DeviceState *dev)
 
 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 {
-#if defined(TARGET_RISCV32)
-    info->print_insn = print_insn_riscv32;
-#elif defined(TARGET_RISCV64)
-    info->print_insn = print_insn_riscv64;
-#endif
+    RISCVCPU *cpu = RISCV_CPU(s);
+    if (riscv_cpu_is_32bit(&cpu->env)) {
+        info->print_insn = print_insn_riscv32;
+    } else {
+        info->print_insn = print_insn_riscv64;
+    }
 }
 
 static void riscv_cpu_realize(DeviceState *dev, Error **errp)