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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec1630ddesm61448235e9.5.2025.04.04.16.56.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 04 Apr 2025 16:56:36 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Eduardo Habkost , qemu-s390x@nongnu.org, Thomas Huth , David Hildenbrand , Zhao Liu , Pierrick Bouvier , Richard Henderson , Anton Johansson , Paolo Bonzini , Riku Voipio , Ilya Leoshkevich , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 2/2] tcg: Convert TARGET_HAS_PRECISE_SMC to TCGCPUOps::has_precise_smc field Date: Sat, 5 Apr 2025 01:56:24 +0200 Message-ID: <20250404235624.67816-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250404235624.67816-1-philmd@linaro.org> References: <20250404235624.67816-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Instead of having a compile-time TARGET_HAS_PRECISE_SMC definition, have targets set the 'has_precise_smc' field in the TCGCPUOps structure. Since so far we only emulate one target architecture at a time, add a static 'tcg_target_has_precise_smc' variable, initialized just after calling TCGCPUOps::initialize() in tcg_exec_realizefn(). Signed-off-by: Philippe Mathieu-Daudé --- include/accel/tcg/cpu-ops.h | 8 ++++++++ include/exec/poison.h | 1 - target/i386/cpu.h | 4 ---- target/s390x/cpu.h | 2 -- accel/tcg/cpu-exec.c | 13 ++++++------- target/i386/tcg/tcg-cpu.c | 1 + target/s390x/cpu.c | 1 + 7 files changed, 16 insertions(+), 14 deletions(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 0e4352513d1..a76cfe49df8 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -28,6 +28,14 @@ struct TCGCPUOps { */ bool mttcg_supported; + /** + * has_precise_smc: guest CPU has precise-SMC semantics + * + * Guest support for precise self modifying code even if the + * modified instruction is close to the modifying instruction. + */ + bool has_precise_smc; + /** * @guest_default_memory_order: default barrier that is required * for the guest memory ordering. diff --git a/include/exec/poison.h b/include/exec/poison.h index 413dfd16f24..011aa2378d7 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -36,7 +36,6 @@ #pragma GCC poison TARGET_HAS_BFLT #pragma GCC poison TARGET_NAME #pragma GCC poison TARGET_BIG_ENDIAN -#pragma GCC poison TARGET_HAS_PRECISE_SMC #pragma GCC poison TARGET_LONG_BITS #pragma GCC poison TARGET_FMT_lx diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 16d76df34b2..5a2e4a8103f 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -35,10 +35,6 @@ #define XEN_NR_VIRQS 24 -/* support for self modifying code even if the modified instruction is - close to the modifying instruction */ -#define TARGET_HAS_PRECISE_SMC - #ifdef TARGET_X86_64 #define I386_ELF_MACHINE EM_X86_64 #define ELF_MACHINE_UNAME "x86_64" diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 90f64ee20cc..ee59039879b 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -35,8 +35,6 @@ #define ELF_MACHINE_UNAME "S390X" -#define TARGET_HAS_PRECISE_SMC - #define MMU_USER_IDX 0 #define S390_MAX_CPUS 248 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index cfe3b93e1e3..d410a4780b3 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -1065,19 +1065,17 @@ int cpu_exec(CPUState *cpu) return ret; } +static bool tcg_target_initialized; +static bool tcg_target_has_precise_smc; + bool target_has_precise_smc(void) { -#ifdef TARGET_HAS_PRECISE_SMC - return true; -#else - return false; -#endif + assert(tcg_target_initialized); + return tcg_target_has_precise_smc; } bool tcg_exec_realizefn(CPUState *cpu, Error **errp) { - static bool tcg_target_initialized; - if (!tcg_target_initialized) { /* Check mandatory TCGCPUOps handlers */ const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; @@ -1088,6 +1086,7 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp) assert(tcg_ops->translate_code); assert(tcg_ops->mmu_index); tcg_ops->initialize(); + tcg_target_has_precise_smc = tcg_ops->has_precise_smc; tcg_target_initialized = true; } diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index a0258f4739e..2254fc2d739 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -130,6 +130,7 @@ static const TCGCPUOps x86_tcg_ops = { * The x86 has a strong memory model with some store-after-load re-ordering */ .guest_default_memory_order = TCG_MO_ALL & ~TCG_MO_ST_LD, + .has_precise_smc = true, .initialize = tcg_x86_init, .translate_code = x86_translate_code, .synchronize_from_tb = x86_cpu_synchronize_from_tb, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 41cccc1e692..845b2515aeb 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -351,6 +351,7 @@ static const TCGCPUOps s390_tcg_ops = { * store-after-load re-ordering. */ .guest_default_memory_order = TCG_MO_ALL & ~TCG_MO_ST_LD, + .has_precise_smc = true, .initialize = s390x_translate_init, .translate_code = s390x_translate_code,