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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c300968a1sm5446597f8f.11.2025.04.04.15.36.06 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 04 Apr 2025 15:36:07 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Gustavo Romero , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 9/9] target/arm: Build Aarch64 gdbstub helpers indistinctly Date: Sat, 5 Apr 2025 00:35:21 +0200 Message-ID: <20250404223521.38781-10-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250404223521.38781-1-philmd@linaro.org> References: <20250404223521.38781-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The Aarch64 gdbstub code is guarded by checks on ARM_FEATURE_AARCH64 and isar_feature_aa64_sve(), only enabled for Aarch64 CPUs. Remove TARGET_AARCH64 #ifdef'ry and build gdbstub64.c once. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/internals.h | 2 +- target/arm/gdbstub.c | 4 ---- target/arm/meson.build | 2 +- 3 files changed, 2 insertions(+), 6 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 5e549b95e14..5fd2631e8e2 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1682,7 +1682,6 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env) return (1ULL << 31) | ((1ULL << pmu_num_counters(env)) - 1); } -#ifdef TARGET_AARCH64 GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cpu, int base_reg); int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg); @@ -1692,6 +1691,7 @@ int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_pauth_reg(CPUState *cs, uint8_t *buf, int reg); int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_tag_ctl_reg(CPUState *cs, uint8_t *buf, int reg); +#ifdef TARGET_AARCH64 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 30068c22627..e76142e8ddb 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -482,10 +482,8 @@ void arm_cpu_register_gdb_commands(ARMCPU *cpu) g_autoptr(GString) qsupported_features = g_string_new(NULL); if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - #ifdef TARGET_AARCH64 aarch64_cpu_register_gdb_commands(cpu, qsupported_features, query_table, set_table); - #endif } /* Set arch-specific handlers for 'q' commands. */ @@ -514,7 +512,6 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) * The lower part of each SVE register aliases to the FPU * registers so we don't need to include both. */ -#ifdef TARGET_AARCH64 if (isar_feature_aa64_sve(&cpu->isar)) { GDBFeature *feature = arm_gen_dynamic_svereg_feature(cs, cs->gdb_num_regs); gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg, @@ -546,7 +543,6 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) gdb_find_static_feature("aarch64-mte.xml"), 0); } -#endif #endif } else { if (arm_feature(env, ARM_FEATURE_NEON)) { diff --git a/target/arm/meson.build b/target/arm/meson.build index 3065081d241..503d106b588 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -3,6 +3,7 @@ arm_ss.add(files( 'cpu.c', 'debug_helper.c', 'gdbstub.c', + 'gdbstub64.c', 'helper.c', 'vfp_fpscr.c', )) @@ -13,7 +14,6 @@ arm_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'cpu64.c', - 'gdbstub64.c', )) arm_system_ss = ss.source_set()