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[92.88.170.184]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c30226b23sm2925910f8f.86.2025.04.03.17.02.16 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 17:02:16 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Pierrick Bouvier , Richard Henderson , Markus Armbruster Subject: [RFC PATCH-for-10.1 36/39] target/arm: Expose Aarch64 helpers indistinctly Date: Fri, 4 Apr 2025 01:58:18 +0200 Message-ID: <20250403235821.9909-37-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403235821.9909-1-philmd@linaro.org> References: <20250403235821.9909-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org At worst, for 32-bit arm binary, using these methods will now produce a link time error, instead of a compile time one. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/internals.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 86577207b85..f9353887415 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1810,7 +1810,6 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env) return (1ULL << 31) | ((1ULL << pmu_num_counters(env)) - 1); } -#ifdef TARGET_AARCH64 GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cpu, int base_reg); int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg); @@ -1828,7 +1827,6 @@ void aarch64_max_tcg_initfn(Object *obj); void aarch64_add_pauth_properties(Object *obj); void aarch64_add_sve_properties(Object *obj); void aarch64_add_sme_properties(Object *obj); -#endif /* Read the CONTROL register as the MRS instruction would. */ uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);