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[92.88.170.184]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c301a6c89sm2946609f8f.28.2025.04.03.17.00.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 17:00:35 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Pierrick Bouvier , Richard Henderson , Markus Armbruster Subject: [RFC PATCH-for-10.1 20/39] target/arm: Extract PSCI definitions to 'psci.h' Date: Fri, 4 Apr 2025 01:58:02 +0200 Message-ID: <20250403235821.9909-21-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403235821.9909-1-philmd@linaro.org> References: <20250403235821.9909-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Extract PSCI definitions (which are not target specific) to the new "target/arm/psci.h", so code from hw/arm/ can use them without having to include the target specific "cpu.h" header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- include/hw/arm/boot.h | 3 ++- target/arm/cpu.h | 6 ------ target/arm/psci.h | 18 ++++++++++++++++++ hw/arm/bananapi_m2u.c | 1 + hw/arm/boot.c | 1 + hw/arm/highbank.c | 1 + hw/arm/imx8mp-evk.c | 1 + hw/arm/mcimx6ul-evk.c | 1 + hw/arm/mcimx7d-sabre.c | 1 + hw/arm/orangepi.c | 1 + hw/arm/sbsa-ref.c | 1 + hw/arm/virt-acpi-build.c | 1 + hw/arm/virt.c | 1 + hw/arm/xlnx-versal-virt.c | 1 + hw/arm/xlnx-zcu102.c | 1 + hw/vmapple/vmapple.c | 1 + target/arm/helper.c | 1 + target/arm/hvf/hvf.c | 1 + target/arm/tcg/op_helper.c | 1 + target/arm/tcg/psci.c | 1 + 20 files changed, 37 insertions(+), 7 deletions(-) create mode 100644 target/arm/psci.h diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h index b12bf61ca81..648fdb88862 100644 --- a/include/hw/arm/boot.h +++ b/include/hw/arm/boot.h @@ -12,6 +12,7 @@ #define HW_ARM_BOOT_H #include "target/arm/cpu-qom.h" +//#include "target/arm/psci.h" #include "qemu/notify.h" typedef enum { @@ -100,7 +101,7 @@ struct arm_boot_info { * as the conduit specifies calls should go to (eg guest firmware booted * to EL3) then PSCI will not be enabled. */ - int psci_conduit; + int psci_conduit;// /* Used internally by arm_boot.c */ int is_linux; hwaddr initrd_start; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0db7292698c..930c5366029 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3104,12 +3104,6 @@ static inline bool bswap_code(bool sctlr_b) void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags); -enum { - QEMU_PSCI_CONDUIT_DISABLED = 0, - QEMU_PSCI_CONDUIT_SMC = 1, - QEMU_PSCI_CONDUIT_HVC = 2, -}; - #ifndef CONFIG_USER_ONLY /* Return the address space index to use for a memory access */ static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) diff --git a/target/arm/psci.h b/target/arm/psci.h new file mode 100644 index 00000000000..8b868dfbb91 --- /dev/null +++ b/target/arm/psci.h @@ -0,0 +1,18 @@ +/* + * ARM Power State Coordination Interface (PSCI) definitions + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef TARGET_ARM_PSCI_H +#define TARGET_ARM_PSCI_H + +enum { + QEMU_PSCI_CONDUIT_DISABLED = 0, + QEMU_PSCI_CONDUIT_SMC = 1, + QEMU_PSCI_CONDUIT_HVC = 2, +}; + +#endif diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c index b750a575f72..61e01a38099 100644 --- a/hw/arm/bananapi_m2u.c +++ b/hw/arm/bananapi_m2u.c @@ -27,6 +27,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/allwinner-r40.h" #include "hw/arm/boot.h" +#include "target/arm/psci.h" static struct arm_boot_info bpim2u_binfo; diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 79afb51b8a5..b81a850819b 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -29,6 +29,7 @@ #include "qemu/config-file.h" #include "qemu/option.h" #include "qemu/units.h" +#include "target/arm/psci.h" /* Kernel boot protocol is specified in the kernel docs * Documentation/arm/Booting and Documentation/arm64/booting.txt diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index 0caa08631ad..16fb2508d30 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -36,6 +36,7 @@ #include "qemu/log.h" #include "qom/object.h" #include "target/arm/cpu-qom.h" +#include "target/arm/psci.h" #define SMP_BOOT_ADDR 0x100 #define SMP_BOOT_REG 0x40 diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c index 6e64ec4ea54..c8a99b2c49e 100644 --- a/hw/arm/imx8mp-evk.c +++ b/hw/arm/imx8mp-evk.c @@ -15,6 +15,7 @@ #include "system/qtest.h" #include "qemu/error-report.h" #include "qapi/error.h" +#include "target/arm/psci.h" static void imx8mp_evk_init(MachineState *machine) { diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c index 86982cb0772..be5e50abf17 100644 --- a/hw/arm/mcimx6ul-evk.c +++ b/hw/arm/mcimx6ul-evk.c @@ -18,6 +18,7 @@ #include "hw/qdev-properties.h" #include "qemu/error-report.h" #include "system/qtest.h" +#include "target/arm/psci.h" static void mcimx6ul_evk_init(MachineState *machine) { diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c index 33119610113..e0f25b92594 100644 --- a/hw/arm/mcimx7d-sabre.c +++ b/hw/arm/mcimx7d-sabre.c @@ -20,6 +20,7 @@ #include "hw/qdev-properties.h" #include "qemu/error-report.h" #include "system/qtest.h" +#include "target/arm/psci.h" static void mcimx7d_sabre_init(MachineState *machine) { diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index e0956880d11..99037a09a36 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -26,6 +26,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/allwinner-h3.h" #include "hw/arm/boot.h" +#include "target/arm/psci.h" static struct arm_boot_info orangepi_binfo; diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 90fbb56ba7a..1f592627c99 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -53,6 +53,7 @@ #include "target/arm/cpu-qom.h" #include "target/arm/gtimer.h" #include "target/arm/multiprocessing.h" +#include "target/arm/psci.h" #define RAMLIMIT_GB 8192 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 3ac8f8e1786..da61af1d359 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -59,6 +59,7 @@ #include "hw/acpi/viot.h" #include "hw/virtio/virtio-acpi.h" #include "target/arm/multiprocessing.h" +#include "target/arm/psci.h" #define ARM_SPI_BASE 32 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index a96452f17a4..fe2dec9500f 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -79,6 +79,7 @@ #include "target/arm/internals.h" #include "target/arm/multiprocessing.h" #include "target/arm/gtimer.h" +#include "target/arm/psci.h" #include "hw/mem/pc-dimm.h" #include "hw/mem/nvdimm.h" #include "hw/acpi/generic_event_device.h" diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index e19c4d9ef58..94fad8e60f2 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -21,6 +21,7 @@ #include "hw/arm/xlnx-versal.h" #include "hw/arm/boot.h" #include "target/arm/multiprocessing.h" +#include "target/arm/psci.h" #include "qom/object.h" #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt") diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 88b1eafab4d..902ee65ca5f 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -26,6 +26,7 @@ #include "qom/object.h" #include "net/can_emu.h" #include "audio/audio.h" +#include "target/arm/psci.h" struct XlnxZCU102 { MachineState parent_obj; diff --git a/hw/vmapple/vmapple.c b/hw/vmapple/vmapple.c index 25652b16f0c..b73b6fb8115 100644 --- a/hw/vmapple/vmapple.c +++ b/hw/vmapple/vmapple.c @@ -53,6 +53,7 @@ #include "system/system.h" #include "target/arm/gtimer.h" #include "target/arm/multiprocessing.h" +#include "target/arm/psci.h" struct VMAppleMachineState { MachineState parent; diff --git a/target/arm/helper.c b/target/arm/helper.c index 7fb6e886306..48238ae0b20 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -34,6 +34,7 @@ #endif #include "cpregs.h" #include "target/arm/gtimer.h" +#include "target/arm/psci.h" #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 34ca36fab55..f617e73feae 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -33,6 +33,7 @@ #include "target/arm/internals.h" #include "target/arm/multiprocessing.h" #include "target/arm/gtimer.h" +#include "target/arm/psci.h" #include "trace.h" #include "migration/vmstate.h" diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 005f84082af..6e9db2e77e2 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -26,6 +26,7 @@ #include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" #include "target/arm/gtimer.h" +#include "target/arm/psci.h" #include "cpregs.h" #define SIGNBIT (uint32_t)0x80000000 diff --git a/target/arm/tcg/psci.c b/target/arm/tcg/psci.c index cabed43e8a8..0313cdd6ba2 100644 --- a/target/arm/tcg/psci.c +++ b/target/arm/tcg/psci.c @@ -25,6 +25,7 @@ #include "internals.h" #include "arm-powerctl.h" #include "target/arm/multiprocessing.h" +#include "target/arm/psci.h" bool arm_is_psci_call(ARMCPU *cpu, int excp_type) {