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[92.88.170.184]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c301b816csm2968052f8f.57.2025.04.03.16.50.08 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 16:50:09 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Markus Armbruster , Richard Henderson , Pierrick Bouvier Subject: [RFC PATCH-for-10.1 08/19] target/riscv: Replace TARGET_LONG_BITS -> target_long_bits() Date: Fri, 4 Apr 2025 01:49:03 +0200 Message-ID: <20250403234914.9154-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403234914.9154-1-philmd@linaro.org> References: <20250403234914.9154-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- hw/riscv/riscv-iommu.c | 3 ++- hw/riscv/riscv_hart.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index 65411b3e4c0..37563b2102f 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -26,6 +26,7 @@ #include "migration/vmstate.h" #include "qapi/error.h" #include "qemu/timer.h" +#include "qemu/target_info.h" #include "cpu_bits.h" #include "riscv-iommu.h" @@ -393,7 +394,7 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx, if (pass == S_STAGE && va_len > 32) { target_ulong mask, masked_msbs; - mask = (1L << (TARGET_LONG_BITS - (va_len - 1))) - 1; + mask = (1L << (target_long_bits() - (va_len - 1))) - 1; masked_msbs = (addr >> (va_len - 1)) & mask; if (masked_msbs != 0 && masked_msbs != mask) { diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index a55d1566687..667d3b0a507 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/module.h" +#include "qemu/target_info.h" #include "system/reset.h" #include "system/qtest.h" #include "qemu/cutils.h" @@ -72,7 +73,7 @@ static void csr_call(char *cmd, uint64_t cpu_num, int csrno, uint64_t *val) ret = riscv_csrr(env, csrno, (target_ulong *)val); } else if (strcmp(cmd, "set_csr") == 0) { ret = riscv_csrrw(env, csrno, NULL, *(target_ulong *)val, - MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); + MAKE_64BIT_MASK(0, target_long_bits())); } g_assert(ret == RISCV_EXCP_NONE);