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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec1795630sm2006255e9.29.2025.04.02.14.05.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Apr 2025 14:05:37 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Subject: [PATCH-for-10.1 26/43] hw/core/cpu: Remove CPUClass::mmu_index() Date: Wed, 2 Apr 2025 23:03:11 +0200 Message-ID: <20250402210328.52897-27-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250402210328.52897-1-philmd@linaro.org> References: <20250402210328.52897-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All targets have been converted to TCGCPUOps::mmu_index(), remove the now unused CPUClass::mmu_index(). Since this handler is now mandatory, add an assertion in tcg_exec_realizefn(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/exec/cpu-mmu-index.h | 4 +--- include/hw/core/cpu.h | 2 -- accel/tcg/cpu-exec.c | 1 + 3 files changed, 2 insertions(+), 5 deletions(-) diff --git a/include/exec/cpu-mmu-index.h b/include/exec/cpu-mmu-index.h index 651526e9f97..a87b6f7c4b7 100644 --- a/include/exec/cpu-mmu-index.h +++ b/include/exec/cpu-mmu-index.h @@ -32,9 +32,7 @@ static inline int cpu_mmu_index(CPUState *cs, bool ifetch) # endif #endif - const TCGCPUOps *tcg_ops = cs->cc->tcg_ops; - int ret = tcg_ops->mmu_index ? tcg_ops->mmu_index(cs, ifetch) - : cs->cc->mmu_index(cs, ifetch); + int ret = cs->cc->tcg_ops->mmu_index(cs, ifetch); tcg_debug_assert(ret >= 0 && ret < NB_MMU_MODES); return ret; } diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 60b7abaf49b..10b6b25b344 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -104,7 +104,6 @@ struct SysemuCPUOps; * instantiatable CPU type. * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. - * @mmu_index: Callback for choosing softmmu mmu index. * @memory_rw_debug: Callback for GDB memory access. * @dump_state: Callback for dumping state. * @query_cpu_fast: @@ -151,7 +150,6 @@ struct CPUClass { ObjectClass *(*class_by_name)(const char *cpu_model); void (*parse_features)(const char *typename, char *str, Error **errp); - int (*mmu_index)(CPUState *cpu, bool ifetch); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, size_t len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 6c6098955f0..5ced3879ac4 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -1076,6 +1076,7 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp) assert(tcg_ops->cpu_exec_interrupt); #endif /* !CONFIG_USER_ONLY */ assert(tcg_ops->translate_code); + assert(tcg_ops->mmu_index); tcg_ops->initialize(); tcg_target_initialized = true; }