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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d43f3328bsm213438795e9.1.2025.03.25.15.43.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 25 Mar 2025 15:43:57 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Thomas Huth , qemu-devel@nongnu.org Cc: Ilya Leoshkevich , BALATON Zoltan , =?utf-8?q?Herv=C3=A9_Poussineau?= , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Matthew Rosato , Gerd Hoffmann , Glenn Miles , Samuel Tardieu , qemu-block@nongnu.org, Patrick Leis , David Hildenbrand , "Edgar E. Iglesias" , Tyrone Ting , Eric Farman , Christian Borntraeger , Peter Maydell , Halil Pasic , Richard Henderson , Kevin Wolf , Alistair Francis , Bernhard Beschow , Hanna Reitz , Hao Wu , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH-for-10.0 08/12] hw/misc/pll: Do not expose as user-creatable Date: Tue, 25 Mar 2025 23:43:06 +0100 Message-ID: <20250325224310.8785-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250325224310.8785-1-philmd@linaro.org> References: <20250325224310.8785-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All these devices are part of SoC components and can not be created manually. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth --- hw/misc/bcm2835_cprman.c | 8 ++++++++ hw/misc/npcm_clk.c | 6 ++++++ hw/misc/stm32l4x5_rcc.c | 4 ++++ 3 files changed, 18 insertions(+) diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c index aa14cd931f5..0c4d4b7de50 100644 --- a/hw/misc/bcm2835_cprman.c +++ b/hw/misc/bcm2835_cprman.c @@ -137,6 +137,8 @@ static void pll_class_init(ObjectClass *klass, void *data) device_class_set_legacy_reset(dc, pll_reset); dc->vmsd = &pll_vmstate; + /* Reason: Part of BCM2835CprmanState component */ + dc->user_creatable = false; } static const TypeInfo cprman_pll_info = { @@ -241,6 +243,8 @@ static void pll_channel_class_init(ObjectClass *klass, void *data) device_class_set_legacy_reset(dc, pll_channel_reset); dc->vmsd = &pll_channel_vmstate; + /* Reason: Part of BCM2835CprmanState component */ + dc->user_creatable = false; } static const TypeInfo cprman_pll_channel_info = { @@ -362,6 +366,8 @@ static void clock_mux_class_init(ObjectClass *klass, void *data) device_class_set_legacy_reset(dc, clock_mux_reset); dc->vmsd = &clock_mux_vmstate; + /* Reason: Part of BCM2835CprmanState component */ + dc->user_creatable = false; } static const TypeInfo cprman_clock_mux_info = { @@ -416,6 +422,8 @@ static void dsi0hsck_mux_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); dc->vmsd = &dsi0hsck_mux_vmstate; + /* Reason: Part of BCM2835CprmanState component */ + dc->user_creatable = false; } static const TypeInfo cprman_dsi0hsck_mux_info = { diff --git a/hw/misc/npcm_clk.c b/hw/misc/npcm_clk.c index 0e85974cf96..b6a893ffb22 100644 --- a/hw/misc/npcm_clk.c +++ b/hw/misc/npcm_clk.c @@ -1108,6 +1108,8 @@ static void npcm7xx_clk_pll_class_init(ObjectClass *klass, void *data) dc->desc = "NPCM7xx Clock PLL Module"; dc->vmsd = &vmstate_npcm7xx_clk_pll; + /* Reason: Part of NPCMCLKState component */ + dc->user_creatable = false; } static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data) @@ -1116,6 +1118,8 @@ static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data) dc->desc = "NPCM7xx Clock SEL Module"; dc->vmsd = &vmstate_npcm7xx_clk_sel; + /* Reason: Part of NPCMCLKState component */ + dc->user_creatable = false; } static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data) @@ -1124,6 +1128,8 @@ static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data) dc->desc = "NPCM7xx Clock Divider Module"; dc->vmsd = &vmstate_npcm7xx_clk_divider; + /* Reason: Part of NPCMCLKState component */ + dc->user_creatable = false; } static void npcm_clk_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/stm32l4x5_rcc.c b/hw/misc/stm32l4x5_rcc.c index fd8466dff34..158b743cae7 100644 --- a/hw/misc/stm32l4x5_rcc.c +++ b/hw/misc/stm32l4x5_rcc.c @@ -150,6 +150,8 @@ static void clock_mux_class_init(ObjectClass *klass, void *data) rc->phases.hold = clock_mux_reset_hold; rc->phases.exit = clock_mux_reset_exit; dc->vmsd = &clock_mux_vmstate; + /* Reason: Part of Stm32l4x5RccState component */ + dc->user_creatable = false; } static void clock_mux_set_enable(RccClockMuxState *mux, bool enabled) @@ -302,6 +304,8 @@ static void pll_class_init(ObjectClass *klass, void *data) rc->phases.hold = pll_reset_hold; rc->phases.exit = pll_reset_exit; dc->vmsd = &pll_vmstate; + /* Reason: Part of Stm32l4x5RccState component */ + dc->user_creatable = false; } static void pll_set_vco_multiplier(RccPllState *pll, uint32_t vco_multiplier)