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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d43f556basm203127755e9.17.2025.03.25.08.41.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 25 Mar 2025 08:41:38 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Eduardo Habkost , Pierrick Bouvier , Zhao Liu , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , =?utf-8?q?Alex_Benn=C3=A9e?= , Anton Johansson Subject: [PATCH-for-10.1 8/8] target/mips: Introduce mips_env_64bit_enabled() helper Date: Tue, 25 Mar 2025 16:40:58 +0100 Message-ID: <20250325154058.92735-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250325154058.92735-1-philmd@linaro.org> References: <20250325154058.92735-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org mips_env_64bit_enabled() returns whether the CPU is running in 32-bit or 64-bit (behavior which might change at runtime). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/mips/internal.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/mips/internal.h b/target/mips/internal.h index 28eb28936ba..8107a59b908 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -225,6 +225,11 @@ static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value) } } +static inline bool mips_env_64bit_enabled(CPUMIPSState *env) +{ + return env->hflags & MIPS_HFLAG_64; +} + static inline bool mips_env_is_bigendian(CPUMIPSState *env) { return extract32(env->CP0_Config0, CP0C0_BE, 1);