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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3997f9b2654sm13458040f8f.41.2025.03.25.05.39.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 25 Mar 2025 05:39:39 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Frederic Konrad , Artyom Tarasenko , Mark Cave-Ayland , =?utf-8?q?Cl=C3=A9ment_Ch?= =?utf-8?q?igot?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH-for-10.1 2/4] target/sparc: Restrict SPARC64 specific features Date: Tue, 25 Mar 2025 13:39:25 +0100 Message-ID: <20250325123927.74939-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250325123927.74939-1-philmd@linaro.org> References: <20250325123927.74939-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Following commit 554abe47c7b ("target/sparc: Partition cpu features"), avoid compiling SPARC64 specific code on 32-bit binary. Signed-off-by: Philippe Mathieu-Daudé --- target/sparc/cpu-feature.h.inc | 20 ++++++++++++-------- target/sparc/translate.c | 10 ++++++++-- 2 files changed, 20 insertions(+), 10 deletions(-) diff --git a/target/sparc/cpu-feature.h.inc b/target/sparc/cpu-feature.h.inc index be810052376..7b7b94a0562 100644 --- a/target/sparc/cpu-feature.h.inc +++ b/target/sparc/cpu-feature.h.inc @@ -1,12 +1,8 @@ FEATURE(FLOAT128) -FEATURE(MUL) -FEATURE(DIV) -FEATURE(VIS1) -FEATURE(VIS2) -FEATURE(FSMULD) -FEATURE(HYPV) -FEATURE(CMT) -FEATURE(GL) +FEATURE(MUL) /* Mandatory in v9 */ +FEATURE(DIV) /* Mandatory in v9 */ +FEATURE(FSMULD) /* Mandatory in v9 */ + FEATURE(TA0_SHUTDOWN) /* Shutdown on "ta 0x0" */ FEATURE(ASR17) FEATURE(CACHE_CTRL) @@ -16,3 +12,11 @@ FEATURE(FMAF) FEATURE(VIS3) FEATURE(IMA) FEATURE(VIS4) + +#ifdef TARGET_SPARC64 +FEATURE(HYPV) +FEATURE(CMT) +FEATURE(GL) +FEATURE(VIS1) +FEATURE(VIS2) +#endif diff --git a/target/sparc/translate.c b/target/sparc/translate.c index bfe63649db2..53b145848b9 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1850,10 +1850,12 @@ static void gen_st_asi(DisasContext *dc, DisasASI *da, TCGv src, TCGv addr) if (TARGET_LONG_BITS == 32) { gen_exception(dc, TT_ILL_INSN); break; +#ifdef TARGET_SPARC64 } else if (!(dc->def->features & CPU_FEATURE_HYPV)) { /* Pre OpenSPARC CPUs don't have these */ gen_exception(dc, TT_ILL_INSN); break; +#endif } /* In OpenSPARC T1+ CPUs TWINX ASIs in store are ST_BLKINIT_ ASIs */ /* fall through */ @@ -2750,12 +2752,16 @@ static bool trans_SETHI(DisasContext *dc, arg_SETHI *a) static bool do_tcc(DisasContext *dc, int cond, int cc, int rs1, bool imm, int rs2_or_imm) { - int mask = ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc) - ? UA2005_HTRAP_MASK : V8_TRAP_MASK); + int mask = 0; DisasCompare cmp; TCGLabel *lab; TCGv_i32 trap; +#ifdef TARGET_SPARC64 + mask = ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc)) + ? UA2005_HTRAP_MASK : V8_TRAP_MASK; +#endif + /* Trap never. */ if (cond == 0) { return advance_pc(dc);