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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 17/17] target/avr: Enable TARGET_PAGE_BITS_VARY Date: Sun, 23 Mar 2025 10:37:29 -0700 Message-ID: <20250323173730.3213964-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Increase TARGET_PHYS_ADDR_SPACE_BITS to allow flexibility in the page size without triggering an assert. Select the page size based on the size of sram. This leaves sram on exactly one page and minimizes the number of pages required to span the flash. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/avr/cpu-param.h | 11 +++++++++-- hw/avr/arduino.c | 15 +++++++++++++++ 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index f5248ce9e7..a18bf39bb9 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -21,8 +21,15 @@ #ifndef AVR_CPU_PARAM_H #define AVR_CPU_PARAM_H -#define TARGET_PAGE_BITS 10 -#define TARGET_PHYS_ADDR_SPACE_BITS 24 +#define TARGET_PAGE_BITS_VARY +#define TARGET_PAGE_BITS_MIN 10 + +/* + * The real value for TARGET_PHYS_ADDR_SPACE_BITS is 24, but selecting + * an overly small value will assert in tb-maint.c when selecting the + * shape of the page_table tree. This allows an 8k page size. + */ +#define TARGET_PHYS_ADDR_SPACE_BITS 28 #define TARGET_VIRT_ADDR_SPACE_BITS 24 #define TCG_GUEST_DEFAULT_MO 0 diff --git a/hw/avr/arduino.c b/hw/avr/arduino.c index 29cb776848..f309aa5597 100644 --- a/hw/avr/arduino.c +++ b/hw/avr/arduino.c @@ -71,9 +71,24 @@ static void arduino_machine_class_init(ObjectClass *oc, void *data) static void arduino_machine_class_base_init(ObjectClass *oc, void *data) { + MachineClass *mc = MACHINE_CLASS(oc); ArduinoMachineClass *amc = ARDUINO_MACHINE_CLASS(oc); + AtmegaMcuClass *acc; + int page_bits; amc->mcu_type = data; + + /* Find the mcu class that we will instantiate. */ + acc = ATMEGA_MCU_CLASS(object_class_by_name(amc->mcu_type)); + + /* + * Select a page size based on the size of sram. + * This will result in a page size between 1k and 8k + * and minimize the number of pages to span flash. + */ + page_bits = ctz32(acc->sram_size); + assert(page_bits >= TARGET_PAGE_BITS_MIN && page_bits <= 13); + mc->minimum_page_bits = page_bits; } static void arduino_duemilanove_class_init(ObjectClass *oc, void *data)