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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 11/17] target/avr: Implement CPUState.memory_rw_debug Date: Sun, 23 Mar 2025 10:37:23 -0700 Message-ID: <20250323173730.3213964-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Prepare for offset_io being non-zero when accessing from gdb. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/avr/cpu.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 080f6f30d3..e4011004b4 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -68,6 +68,35 @@ static void avr_restore_state_to_opc(CPUState *cs, cpu_env(cs)->pc_w = data[0]; } +static int avr_memory_rw_debug(CPUState *cpu, vaddr addr, + uint8_t *buf, size_t len, bool is_write) +{ + if (addr < OFFSET_DATA) { + size_t len_code; + int ret; + + if (addr + len <= OFFSET_DATA) { + return cpu_memory_rw_debug(cpu, addr, buf, len, is_write); + } + + len_code = addr + len - OFFSET_DATA; + ret = cpu_memory_rw_debug(cpu, addr, buf, len_code, is_write); + if (ret != 0) { + return ret; + } + addr = OFFSET_DATA; + len -= len_code; + } + + /* + * Data is biased such that SRAM begins at TARGET_PAGE_SIZE, + * and I/O is immediately prior. This leave a hole between + * OFFSET_DATA and the relative start of the address space. + */ + addr += env_archcpu(cpu_env(cpu))->offset_io; + return cpu_memory_rw_debug(cpu, addr, buf, len, is_write); +} + static void avr_cpu_reset_hold(Object *obj, ResetType type) { CPUState *cs = CPU(obj); @@ -262,6 +291,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_write_register = avr_cpu_gdb_write_register; cc->gdb_adjust_breakpoint = avr_cpu_gdb_adjust_breakpoint; cc->gdb_core_xml_file = "avr-cpu.xml"; + cc->memory_rw_debug = avr_memory_rw_debug; cc->tcg_ops = &avr_tcg_ops; }