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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-391188029e0sm5643708f8f.52.2025.03.05.07.39.58 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 05 Mar 2025 07:39:59 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Paolo Bonzini , Richard Henderson , Pierrick Bouvier , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Subject: [RFC PATCH 06/18] hw/mips/mipssim: Replace TARGET_MIPS64 by legacy_binary_is_64bit() Date: Wed, 5 Mar 2025 16:39:16 +0100 Message-ID: <20250305153929.43687-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250305153929.43687-1-philmd@linaro.org> References: <20250305153929.43687-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For legacy MIPS binaries, legacy_binary_is_64bit() is equivalent of the compile time TARGET_MIPS64 definition. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/mipssim.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c index c530688e769..f94dbdc428b 100644 --- a/hw/mips/mipssim.c +++ b/hw/mips/mipssim.c @@ -28,6 +28,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/datadir.h" +#include "qemu/legacy_binary_info.h" #include "exec/address-spaces.h" #include "hw/clock.h" #include "hw/mips/mips.h" @@ -152,13 +153,10 @@ mips_mipssim_init(MachineState *machine) CPUMIPSState *env; ResetData *reset_info; int bios_size; + unsigned clock_hz = (legacy_binary_is_64bit() ? 6 : 12) * 1000 * 1000; cpuclk = clock_new(OBJECT(machine), "cpu-refclk"); -#ifdef TARGET_MIPS64 - clock_set_hz(cpuclk, 6000000); /* 6 MHz */ -#else - clock_set_hz(cpuclk, 12000000); /* 12 MHz */ -#endif + clock_set_hz(cpuclk, clock_hz); /* Init CPUs. */ cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, @@ -241,11 +239,8 @@ static void mips_mipssim_machine_init(MachineClass *mc) { mc->desc = "MIPS MIPSsim platform"; mc->init = mips_mipssim_init; -#ifdef TARGET_MIPS64 - mc->default_cpu_type = MIPS_CPU_TYPE_NAME("5Kf"); -#else - mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf"); -#endif + mc->default_cpu_type = legacy_binary_is_64bit() ? MIPS_CPU_TYPE_NAME("5Kf") + : MIPS_CPU_TYPE_NAME("24Kf"); mc->default_ram_id = "mips_mipssim.ram"; }