[v3,8/9] hw/arm: enable secure EL2 timers for virt machine

Message ID	20250204125009.2281315-9-peter.maydell@linaro.org
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Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Peter Maydell <peter.maydell@linaro.org> To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= <alex.bennee@linaro.org> Subject: [PATCH v3 8/9] hw/arm: enable secure EL2 timers for virt machine Date: Tue, 4 Feb 2025 12:50:08 +0000 Message-Id: <20250204125009.2281315-9-peter.maydell@linaro.org> In-Reply-To: <20250204125009.2281315-1-peter.maydell@linaro.org> References: <20250204125009.2281315-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	target/arm: Implement SEL2 physical and virtual timers \| expand [v3,0/9] target/arm: Implement SEL2 physical and virtual timers [v3,1/9] target/arm: Apply correct timer offset when calculating deadlines [v3,2/9] target/arm: Don't apply CNTVOFF_EL2 for EL2_VIRT timer [v3,3/9] target/arm: Make CNTPS_* UNDEF from Secure EL1 when Secure EL2 is enabled [v3,4/9] target/arm: Always apply CNTVOFF_EL2 for CNTV_TVAL_EL02 accesses [v3,5/9] target/arm: Refactor handling of timer offset for direct register accesses [v3,6/9] target/arm: Implement SEL2 physical and virtual timers [v3,7/9] target/arm: document the architectural names of our GTIMERs [v3,8/9] hw/arm: enable secure EL2 timers for virt machine [v3,9/9] hw/arm: enable secure EL2 timers for sbsa machine

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Subject: [PATCH v3 8/9] hw/arm: enable secure EL2 timers for virt machine
Date: Tue,  4 Feb 2025 12:50:08 +0000
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Series

target/arm: Implement SEL2 physical and virtual timers | expand

Commit Message

Peter Maydell Feb. 4, 2025, 12:50 p.m. UTC

From: Alex Bennée <alex.bennee@linaro.org>

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 99e0a68b6c5..c00a6e410cd 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -873,6 +873,8 @@  static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
             [GTIMER_HYP]  = ARCH_TIMER_NS_EL2_IRQ,
             [GTIMER_SEC]  = ARCH_TIMER_S_EL1_IRQ,
             [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
+            [GTIMER_S_EL2_PHYS] = ARCH_TIMER_S_EL2_IRQ,
+            [GTIMER_S_EL2_VIRT] = ARCH_TIMER_S_EL2_VIRT_IRQ,
         };
 
         for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {

[v3,8/9] hw/arm: enable secure EL2 timers for virt machine

Commit Message

Patch