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[71.212.32.190]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21da3ea4200sm89341745ad.88.2025.01.28.17.39.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jan 2025 17:39:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH v2 29/34] Revert "target/arm: Handle FPCR.AH in FMLSL" Date: Tue, 28 Jan 2025 17:38:52 -0800 Message-ID: <20250129013857.135256-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250129013857.135256-1-richard.henderson@linaro.org> References: <20250129013857.135256-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This reverts commit c5eb0b62e603c1d391ee2199108f0eb34aadc8f5. --- target/arm/tcg/translate-a64.c | 4 ++-- target/arm/tcg/vec_helper.c | 28 ++++------------------------ 2 files changed, 6 insertions(+), 26 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 9b1675b041..d27b4e964d 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -5997,7 +5997,7 @@ TRANS(FMINNMP_v, do_fp3_vector, a, 0, f_vector_fminnmp) static bool do_fmlal(DisasContext *s, arg_qrrr_e *a, bool is_s, bool is_2) { if (fp_access_check(s)) { - int data = (s->fpcr_ah << 2) | (is_2 << 1) | is_s; + int data = (is_2 << 1) | is_s; tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), vec_full_reg_offset(s, a->rm), tcg_env, @@ -6772,7 +6772,7 @@ TRANS(FMLS_vi, do_fmla_vector_idx, a, true) static bool do_fmlal_idx(DisasContext *s, arg_qrrx_e *a, bool is_s, bool is_2) { if (fp_access_check(s)) { - int data = (s->fpcr_ah << 5) | (a->idx << 2) | (is_2 << 1) | is_s; + int data = (a->idx << 2) | (is_2 << 1) | is_s; tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), vec_full_reg_offset(s, a->rm), tcg_env, diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 728473e919..b3ed6533bb 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -2120,26 +2120,6 @@ static uint64_t load4_f16(uint64_t *ptr, int is_q, int is_2) return ptr[is_q & is_2] >> ((is_2 & ~is_q) << 5); } -static uint64_t neg4_f16(uint64_t v, bool fpcr_ah) -{ - /* - * Negate all inputs for FMLSL at once. This is slightly complicated - * by the need to avoid flipping the sign of a NaN when FPCR.AH == 1 - */ - uint64_t mask = 0x8000800080008000ull; - if (fpcr_ah) { - uint64_t tmp = v, signbit = 0x8000; - for (int i = 0; i < 4; i++) { - if (float16_is_any_nan(extract64(tmp, 0, 16))) { - mask ^= signbit; - } - tmp >>= 16; - signbit <<= 16; - } - } - return v ^ mask; -} - /* * Note that FMLAL requires oprsz == 8 or oprsz == 16, * as there is not yet SVE versions that might use blocking. @@ -2151,7 +2131,6 @@ static void do_fmlal(float32 *d, void *vn, void *vm, float_status *fpst, intptr_t i, oprsz = simd_oprsz(desc); int is_s = extract32(desc, SIMD_DATA_SHIFT, 1); int is_2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1); - bool fpcr_ah = extract32(desc, SIMD_DATA_SHIFT + 2, 1); int is_q = oprsz == 16; uint64_t n_4, m_4; @@ -2159,8 +2138,9 @@ static void do_fmlal(float32 *d, void *vn, void *vm, float_status *fpst, n_4 = load4_f16(vn, is_q, is_2); m_4 = load4_f16(vm, is_q, is_2); + /* Negate all inputs for FMLSL at once. */ if (is_s) { - n_4 = neg4_f16(n_4, fpcr_ah); + n_4 ^= 0x8000800080008000ull; } for (i = 0; i < oprsz / 4; i++) { @@ -2212,7 +2192,6 @@ static void do_fmlal_idx(float32 *d, void *vn, void *vm, float_status *fpst, int is_s = extract32(desc, SIMD_DATA_SHIFT, 1); int is_2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1); int index = extract32(desc, SIMD_DATA_SHIFT + 2, 3); - bool fpcr_ah = extract32(desc, SIMD_DATA_SHIFT + 5, 1); int is_q = oprsz == 16; uint64_t n_4; float32 m_1; @@ -2220,8 +2199,9 @@ static void do_fmlal_idx(float32 *d, void *vn, void *vm, float_status *fpst, /* Pre-load all of the f16 data, avoiding overlap issues. */ n_4 = load4_f16(vn, is_q, is_2); + /* Negate all inputs for FMLSL at once. */ if (is_s) { - n_4 = neg4_f16(n_4, fpcr_ah); + n_4 ^= 0x8000800080008000ull; } m_1 = float16_to_float32_by_bits(((float16 *)vm)[H2(index)], fz16);