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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd47eecasm31683025e9.6.2025.01.24.08.29.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 08:29:00 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 19/76] fpu: Rename float_flag_input_denormal to float_flag_input_denormal_flushed Date: Fri, 24 Jan 2025 16:27:39 +0000 Message-Id: <20250124162836.2332150-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250124162836.2332150-1-peter.maydell@linaro.org> References: <20250124162836.2332150-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Our float_flag_input_denormal exception flag is set when the fpu code flushes an input denormal to zero. This is what many guest architectures (eg classic Arm behaviour) require, but it is not the only donarmal-related reason we might want to set an exception flag. The x86 behaviour (which we do not currently model correctly) wants to see an exception flag when a denormal input is *not* flushed to zero and is actually used in an arithmetic operation. Arm's FEAT_AFP also wants these semantics. Rename float_flag_input_denormal to float_flag_input_denormal_flushed to make it clearer when it is set and to allow us to add a new float_flag_input_denormal_used next to it for the x86/FEAT_AFP semantics. Commit created with for f in `git grep -l float_flag_input_denormal`; do sed -i -e 's/float_flag_input_denormal/float_flag_input_denormal_flushed/' $f; done and manual editing of softfloat-types.h and softfloat.c to clean up the indentation afterwards and to fix a comment which wasn't using the full name of the flag. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/fpu/softfloat-types.h | 5 +++-- fpu/softfloat.c | 4 ++-- target/arm/tcg/sve_helper.c | 6 +++--- target/arm/vfp_helper.c | 10 +++++----- target/i386/tcg/fpu_helper.c | 6 +++--- target/mips/tcg/msa_helper.c | 2 +- target/rx/op_helper.c | 2 +- fpu/softfloat-parts.c.inc | 2 +- 8 files changed, 19 insertions(+), 18 deletions(-) diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index d8f831c331d..77bc172a074 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -154,7 +154,8 @@ enum { float_flag_overflow = 0x0004, float_flag_underflow = 0x0008, float_flag_inexact = 0x0010, - float_flag_input_denormal = 0x0020, + /* We flushed an input denormal to 0 (because of flush_inputs_to_zero) */ + float_flag_input_denormal_flushed = 0x0020, float_flag_output_denormal = 0x0040, float_flag_invalid_isi = 0x0080, /* inf - inf */ float_flag_invalid_imz = 0x0100, /* inf * 0 */ @@ -312,7 +313,7 @@ typedef struct float_status { bool tininess_before_rounding; /* should denormalised results go to zero and set the inexact flag? */ bool flush_to_zero; - /* should denormalised inputs go to zero and set the input_denormal flag? */ + /* should denormalised inputs go to zero and set input_denormal_flushed? */ bool flush_inputs_to_zero; bool default_nan_mode; /* diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 8d75d668172..648050be6fb 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -132,7 +132,7 @@ this code that are retained. if (unlikely(soft_t ## _is_denormal(*a))) { \ *a = soft_t ## _set_sign(soft_t ## _zero, \ soft_t ## _is_neg(*a)); \ - float_raise(float_flag_input_denormal, s); \ + float_raise(float_flag_input_denormal_flushed, s); \ } \ } @@ -4848,7 +4848,7 @@ float128 float128_silence_nan(float128 a, float_status *status) static bool parts_squash_denormal(FloatParts64 p, float_status *status) { if (p.exp == 0 && p.frac != 0) { - float_raise(float_flag_input_denormal, status); + float_raise(float_flag_input_denormal_flushed, status); return true; } diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index d0865dece35..9837c5bc7ac 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -4658,7 +4658,7 @@ static int16_t do_float16_logb_as_int(float16 a, float_status *s) return -15 - clz32(frac); } /* flush to zero */ - float_raise(float_flag_input_denormal, s); + float_raise(float_flag_input_denormal_flushed, s); } } else if (unlikely(exp == 0x1f)) { if (frac == 0) { @@ -4686,7 +4686,7 @@ static int32_t do_float32_logb_as_int(float32 a, float_status *s) return -127 - clz32(frac); } /* flush to zero */ - float_raise(float_flag_input_denormal, s); + float_raise(float_flag_input_denormal_flushed, s); } } else if (unlikely(exp == 0xff)) { if (frac == 0) { @@ -4714,7 +4714,7 @@ static int64_t do_float64_logb_as_int(float64 a, float_status *s) return -1023 - clz64(frac); } /* flush to zero */ - float_raise(float_flag_input_denormal, s); + float_raise(float_flag_input_denormal_flushed, s); } } else if (unlikely(exp == 0x7ff)) { if (frac == 0) { diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 3ed69d73698..444702a4600 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -53,7 +53,7 @@ static inline uint32_t vfp_exceptbits_from_host(int host_bits) if (host_bits & float_flag_inexact) { target_bits |= FPSR_IXC; } - if (host_bits & float_flag_input_denormal) { + if (host_bits & float_flag_input_denormal_flushed) { target_bits |= FPSR_IDC; } return target_bits; @@ -68,11 +68,11 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env) i |= get_float_exception_flags(&env->vfp.standard_fp_status); /* FZ16 does not generate an input denormal exception. */ i |= (get_float_exception_flags(&env->vfp.fp_status_f16_a32) - & ~float_flag_input_denormal); + & ~float_flag_input_denormal_flushed); i |= (get_float_exception_flags(&env->vfp.fp_status_f16_a64) - & ~float_flag_input_denormal); + & ~float_flag_input_denormal_flushed); i |= (get_float_exception_flags(&env->vfp.standard_fp_status_f16) - & ~float_flag_input_denormal); + & ~float_flag_input_denormal_flushed); return vfp_exceptbits_from_host(i); } @@ -1133,7 +1133,7 @@ uint64_t HELPER(fjcvtzs)(float64 value, float_status *status) /* Normal inexact, denormal with flush-to-zero, or overflow or NaN */ inexact = e_new & (float_flag_inexact | - float_flag_input_denormal | + float_flag_input_denormal_flushed | float_flag_invalid); /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */ diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index e0a072b4ebc..7151e809643 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -207,7 +207,7 @@ static void merge_exception_flags(CPUX86State *env, uint8_t old_flags) (new_flags & float_flag_overflow ? FPUS_OE : 0) | (new_flags & float_flag_underflow ? FPUS_UE : 0) | (new_flags & float_flag_inexact ? FPUS_PE : 0) | - (new_flags & float_flag_input_denormal ? FPUS_DE : 0))); + (new_flags & float_flag_input_denormal_flushed ? FPUS_DE : 0))); } static inline floatx80 helper_fdiv(CPUX86State *env, floatx80 a, floatx80 b) @@ -1832,7 +1832,7 @@ void helper_fxtract(CPUX86State *env) int shift = clz64(temp.l.lower); temp.l.lower <<= shift; expdif = 1 - EXPBIAS - shift; - float_raise(float_flag_input_denormal, &env->fp_status); + float_raise(float_flag_input_denormal_flushed, &env->fp_status); } else { expdif = EXPD(temp) - EXPBIAS; } @@ -3261,7 +3261,7 @@ void update_mxcsr_from_sse_status(CPUX86State *env) uint8_t flags = get_float_exception_flags(&env->sse_status); /* * The MXCSR denormal flag has opposite semantics to - * float_flag_input_denormal (the softfloat code sets that flag + * float_flag_input_denormal_flushed (the softfloat code sets that flag * only when flushing input denormals to zero, but SSE sets it * only when not flushing them to zero), so is not converted * here. diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index 1d40383ca4f..aeab6a1d8b3 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -6231,7 +6231,7 @@ static inline int update_msacsr(CPUMIPSState *env, int action, int denormal) enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED; /* Set Inexact (I) when flushing inputs to zero */ - if ((ieee_exception_flags & float_flag_input_denormal) && + if ((ieee_exception_flags & float_flag_input_denormal_flushed) && (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) { if (action & CLEAR_IS_INEXACT) { mips_exception_flags &= ~FP_INEXACT; diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c index 691a12b2be1..59dd1ae6128 100644 --- a/target/rx/op_helper.c +++ b/target/rx/op_helper.c @@ -99,7 +99,7 @@ static void update_fpsw(CPURXState *env, float32 ret, uintptr_t retaddr) if (xcpt & float_flag_inexact) { SET_FPSW(X); } - if ((xcpt & (float_flag_input_denormal + if ((xcpt & (float_flag_input_denormal_flushed | float_flag_output_denormal)) && !FIELD_EX32(env->fpsw, FPSW, DN)) { env->fpsw = FIELD_DP32(env->fpsw, FPSW, CE, 1); diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 4bb341b2f94..ec2467e9fff 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -199,7 +199,7 @@ static void partsN(canonicalize)(FloatPartsN *p, float_status *status, if (likely(frac_eqz(p))) { p->cls = float_class_zero; } else if (status->flush_inputs_to_zero) { - float_raise(float_flag_input_denormal, status); + float_raise(float_flag_input_denormal_flushed, status); p->cls = float_class_zero; frac_clear(p); } else {