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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c2a17d6e2sm802184f8f.23.2025.01.23.13.57.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Jan 2025 13:57:25 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Harsh Prateek Bora , Richard Henderson , qemu-ppc@nongnu.org, Nicholas Piggin , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 15/15] target/ppc: Restrict ATTN helper to TCG Date: Thu, 23 Jan 2025 22:56:09 +0100 Message-ID: <20250123215609.30432-16-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250123215609.30432-1-philmd@linaro.org> References: <20250123215609.30432-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move helper_attn() to tcg-excp_helper.c and make raise_exception_err() static. Signed-off-by: Philippe Mathieu-Daudé --- target/ppc/cpu.h | 2 -- target/ppc/excp_helper.c | 20 -------------------- target/ppc/tcg-excp_helper.c | 13 ++++++++++++- 3 files changed, 12 insertions(+), 23 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index ca5bbd263cb..35b56368eac 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2752,8 +2752,6 @@ static inline void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, } #endif -G_NORETURN void raise_exception_err(CPUPPCState *env, uint32_t exception, - uint32_t error_code); G_NORETURN void raise_exception_err_ra(CPUPPCState *env, uint32_t exception, uint32_t error_code, uintptr_t raddr); diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 2d4d47ee384..eedfa2d1de1 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -31,11 +31,6 @@ #include "trace.h" -#ifdef CONFIG_TCG -#include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" -#endif - /*****************************************************************************/ /* Exception processing */ #ifndef CONFIG_USER_ONLY @@ -400,21 +395,6 @@ static void powerpc_set_excp_state(PowerPCCPU *cpu, target_ulong vector, env->reserve_addr = -1; } -#ifdef CONFIG_TCG -#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) -void helper_attn(CPUPPCState *env) -{ - /* POWER attn is unprivileged when enabled by HID, otherwise illegal */ - if ((*env->check_attn)(env)) { - powerpc_checkstop(env, "host executed attn"); - } else { - raise_exception_err(env, POWERPC_EXCP_HV_EMU, - POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); - } -} -#endif -#endif /* CONFIG_TCG */ - static void powerpc_mcheck_checkstop(CPUPPCState *env) { /* KVM guests always have MSR[ME] enabled */ diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c index 072a7fd0947..b6765835683 100644 --- a/target/ppc/tcg-excp_helper.c +++ b/target/ppc/tcg-excp_helper.c @@ -56,7 +56,7 @@ void helper_raise_exception(CPUPPCState *env, uint32_t exception) #ifndef CONFIG_USER_ONLY -void raise_exception_err(CPUPPCState *env, uint32_t exception, +static G_NORETURN void raise_exception_err(CPUPPCState *env, uint32_t exception, uint32_t error_code) { raise_exception_err_ra(env, exception, error_code, 0); @@ -544,6 +544,17 @@ void helper_pminsn(CPUPPCState *env, uint32_t insn) ppc_maybe_interrupt(env); } +void helper_attn(CPUPPCState *env) +{ + /* POWER attn is unprivileged when enabled by HID, otherwise illegal */ + if ((*env->check_attn)(env)) { + powerpc_checkstop(env, "host executed attn"); + } else { + raise_exception_err(env, POWERPC_EXCP_HV_EMU, + POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); + } +} + #endif /* TARGET_PPC64 */ static void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)