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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43890468c67sm187575405e9.34.2025.01.21.08.18.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 21 Jan 2025 08:18:42 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Aleksandar Rikalo , Jiaxun Yang , Bernhard Beschow , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Huacai Chen , Aurelien Jarno Subject: [PATCH 5/6] target/mips: Move CPU timer from hw/mips/ to target/mips/system/ Date: Tue, 21 Jan 2025 17:18:16 +0100 Message-ID: <20250121161817.33654-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250121161817.33654-1-philmd@linaro.org> References: <20250121161817.33654-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org MIPS CPU timer is tied to the CPU, no point of modelling it as a general timer device. Move mips_int.c to target/mips/system/. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/mips/mips_int.c => target/mips/system/interrupts.c | 0 hw/mips/meson.build | 2 +- target/mips/system/meson.build | 1 + 3 files changed, 2 insertions(+), 1 deletion(-) rename hw/mips/mips_int.c => target/mips/system/interrupts.c (100%) diff --git a/hw/mips/mips_int.c b/target/mips/system/interrupts.c similarity index 100% rename from hw/mips/mips_int.c rename to target/mips/system/interrupts.c diff --git a/hw/mips/meson.build b/hw/mips/meson.build index fcbee53bb32..6dd97331ca7 100644 --- a/hw/mips/meson.build +++ b/hw/mips/meson.build @@ -1,5 +1,5 @@ mips_ss = ss.source_set() -mips_ss.add(files('bootloader.c', 'mips_int.c')) +mips_ss.add(files('bootloader.c')) common_ss.add(when: 'CONFIG_FW_CFG_MIPS', if_true: files('fw_cfg.c')) mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c', 'loongson3_virt.c')) mips_ss.add(when: 'CONFIG_MALTA', if_true: files('malta.c')) diff --git a/target/mips/system/meson.build b/target/mips/system/meson.build index 498cf289d6f..cf232c9edad 100644 --- a/target/mips/system/meson.build +++ b/target/mips/system/meson.build @@ -2,6 +2,7 @@ mips_system_ss.add(files( 'addr.c', 'cp0.c', 'cp0_timer.c', + 'interrupts.c', 'machine.c', 'mips-qmp-cmds.c', 'physaddr.c',