Message ID | 20250121161817.33654-6-philmd@linaro.org |
---|---|
State | New |
Headers | show |
Series | target/mips: Convert legacy qemu_allocate_irqs() to qemu_init_irq() | expand |
On 1/21/25 08:18, Philippe Mathieu-Daudé wrote: > MIPS CPU timer is tied to the CPU, no point of modelling it as > a general timer device. Move mips_int.c to target/mips/system/. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > hw/mips/mips_int.c => target/mips/system/interrupts.c | 0 > hw/mips/meson.build | 2 +- > target/mips/system/meson.build | 1 + > 3 files changed, 2 insertions(+), 1 deletion(-) > rename hw/mips/mips_int.c => target/mips/system/interrupts.c (100%) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ > > diff --git a/hw/mips/mips_int.c b/target/mips/system/interrupts.c > similarity index 100% > rename from hw/mips/mips_int.c > rename to target/mips/system/interrupts.c > diff --git a/hw/mips/meson.build b/hw/mips/meson.build > index fcbee53bb32..6dd97331ca7 100644 > --- a/hw/mips/meson.build > +++ b/hw/mips/meson.build > @@ -1,5 +1,5 @@ > mips_ss = ss.source_set() > -mips_ss.add(files('bootloader.c', 'mips_int.c')) > +mips_ss.add(files('bootloader.c')) > common_ss.add(when: 'CONFIG_FW_CFG_MIPS', if_true: files('fw_cfg.c')) > mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c', 'loongson3_virt.c')) > mips_ss.add(when: 'CONFIG_MALTA', if_true: files('malta.c')) > diff --git a/target/mips/system/meson.build b/target/mips/system/meson.build > index 498cf289d6f..cf232c9edad 100644 > --- a/target/mips/system/meson.build > +++ b/target/mips/system/meson.build > @@ -2,6 +2,7 @@ mips_system_ss.add(files( > 'addr.c', > 'cp0.c', > 'cp0_timer.c', > + 'interrupts.c', > 'machine.c', > 'mips-qmp-cmds.c', > 'physaddr.c',
diff --git a/hw/mips/mips_int.c b/target/mips/system/interrupts.c similarity index 100% rename from hw/mips/mips_int.c rename to target/mips/system/interrupts.c diff --git a/hw/mips/meson.build b/hw/mips/meson.build index fcbee53bb32..6dd97331ca7 100644 --- a/hw/mips/meson.build +++ b/hw/mips/meson.build @@ -1,5 +1,5 @@ mips_ss = ss.source_set() -mips_ss.add(files('bootloader.c', 'mips_int.c')) +mips_ss.add(files('bootloader.c')) common_ss.add(when: 'CONFIG_FW_CFG_MIPS', if_true: files('fw_cfg.c')) mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c', 'loongson3_virt.c')) mips_ss.add(when: 'CONFIG_MALTA', if_true: files('malta.c')) diff --git a/target/mips/system/meson.build b/target/mips/system/meson.build index 498cf289d6f..cf232c9edad 100644 --- a/target/mips/system/meson.build +++ b/target/mips/system/meson.build @@ -2,6 +2,7 @@ mips_system_ss.add(files( 'addr.c', 'cp0.c', 'cp0_timer.c', + 'interrupts.c', 'machine.c', 'mips-qmp-cmds.c', 'physaddr.c',
MIPS CPU timer is tied to the CPU, no point of modelling it as a general timer device. Move mips_int.c to target/mips/system/. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- hw/mips/mips_int.c => target/mips/system/interrupts.c | 0 hw/mips/meson.build | 2 +- target/mips/system/meson.build | 1 + 3 files changed, 2 insertions(+), 1 deletion(-) rename hw/mips/mips_int.c => target/mips/system/interrupts.c (100%)