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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-437c74ac61csm244464805e9.14.2025.01.21.08.18.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 21 Jan 2025 08:18:37 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Aleksandar Rikalo , Jiaxun Yang , Bernhard Beschow , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Huacai Chen , Aurelien Jarno Subject: [PATCH 4/6] target/mips: Pass env to cpu_mips_clock_init() Date: Tue, 21 Jan 2025 17:18:15 +0100 Message-ID: <20250121161817.33654-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250121161817.33654-1-philmd@linaro.org> References: <20250121161817.33654-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Simplify cpu_mips_clock_init() by having it directly take a CPU env, move its declaration from "cpu.h" to "internal.h", as it shouldn't be accessible from hw/. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu.h | 1 - target/mips/internal.h | 1 + target/mips/cpu.c | 2 +- target/mips/system/cp0_timer.c | 4 +--- 4 files changed, 3 insertions(+), 5 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index f6877ece8b4..e5767ea9cf3 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1361,7 +1361,6 @@ uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr); /* HW declaration specific to the MIPS target */ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); void cpu_mips_irq_init_cpu(MIPSCPU *cpu); -void cpu_mips_clock_init(MIPSCPU *cpu); #endif /* !CONFIG_USER_ONLY */ diff --git a/target/mips/internal.h b/target/mips/internal.h index 28eb28936ba..69452aae5bc 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -214,6 +214,7 @@ void cpu_mips_store_count(CPUMIPSState *env, uint32_t value); void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value); void cpu_mips_start_count(CPUMIPSState *env); void cpu_mips_stop_count(CPUMIPSState *env); +void cpu_mips_clock_init(CPUMIPSState *env); static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value) { diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 95df8985bc6..99f442a4b98 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -479,7 +479,7 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp) /* Init internal devices */ #ifndef CONFIG_USER_ONLY cpu_mips_irq_init_cpu(cpu); - cpu_mips_clock_init(cpu); + cpu_mips_clock_init(env); #endif if (!clock_get(cpu->clock)) { #ifndef CONFIG_USER_ONLY diff --git a/target/mips/system/cp0_timer.c b/target/mips/system/cp0_timer.c index ca16945cee1..07641cab521 100644 --- a/target/mips/system/cp0_timer.c +++ b/target/mips/system/cp0_timer.c @@ -133,10 +133,8 @@ static void mips_timer_cb(void *opaque) cpu_mips_timer_expire(env); } -void cpu_mips_clock_init(MIPSCPU *cpu) +void cpu_mips_clock_init(CPUMIPSState *env) { - CPUMIPSState *env = &cpu->env; - /* * If we're in KVM mode, don't create the periodic timer, that is handled in * kernel.