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[174.21.71.127]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21c2d3acccesm18879005ad.123.2025.01.17.10.25.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jan 2025 10:25:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 37/68] tcg: Remove args_ct from TCGOpDef Date: Fri, 17 Jan 2025 10:24:25 -0800 Message-ID: <20250117182456.2077110-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250117182456.2077110-1-richard.henderson@linaro.org> References: <20250117182456.2077110-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Introduce a new function, opcode_args_ct, to look up the argument set for an opcode. We lose the ability to assert the correctness of the map from TCGOpcode to constraint sets at startup, but we can still validate at runtime upon lookup. Rename process_op_defs to process_constraint_sets, as it now does nothing to TCGOpDef. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 1 - tcg/tcg-common.c | 2 +- tcg/tcg.c | 82 ++++++++++++++++++++++------------------------- 3 files changed, 40 insertions(+), 45 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index a02de82508..e28894c57b 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -714,7 +714,6 @@ typedef struct TCGOpDef { const char *name; uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args; uint8_t flags; - const TCGArgConstraint *args_ct; } TCGOpDef; extern TCGOpDef tcg_op_defs[]; diff --git a/tcg/tcg-common.c b/tcg/tcg-common.c index fadc33c3d1..0f30e5b3ec 100644 --- a/tcg/tcg-common.c +++ b/tcg/tcg-common.c @@ -28,7 +28,7 @@ TCGOpDef tcg_op_defs[] = { #define DEF(s, oargs, iargs, cargs, flags) \ - { #s, oargs, iargs, cargs, iargs + oargs + cargs, flags, NULL }, + { #s, oargs, iargs, cargs, iargs + oargs + cargs, flags }, #include "tcg/tcg-opc.h" #undef DEF }; diff --git a/tcg/tcg.c b/tcg/tcg.c index d5ab0abe9d..df7c4dab88 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1496,7 +1496,7 @@ static void init_call_layout(TCGHelperInfo *info) } static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)]; -static void process_op_defs(TCGContext *s); +static void process_constraint_sets(void); static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, TCGReg reg, const char *name); @@ -1517,7 +1517,7 @@ static void tcg_context_init(unsigned max_cpus) init_call_layout(&info_helper_st128_mmu); tcg_target_init(s); - process_op_defs(s); + process_constraint_sets(); /* Reverse the order of the saved registers, assuming they're all at the start of tcg_target_reg_alloc_order. */ @@ -3176,7 +3176,7 @@ static void sort_constraints(TCGArgConstraint *a, int start, int n) static const TCGArgConstraint empty_cts[TCG_MAX_OP_ARGS]; static TCGArgConstraint all_cts[ARRAY_SIZE(constraint_sets)][TCG_MAX_OP_ARGS]; -static void process_op_defs(TCGContext *s) +static void process_constraint_sets(void) { for (size_t c = 0; c < ARRAY_SIZE(constraint_sets); ++c) { const TCGConstraintSet *tdefs = &constraint_sets[c]; @@ -3360,38 +3360,28 @@ static void process_op_defs(TCGContext *s) sort_constraints(args_ct, 0, nb_oargs); sort_constraints(args_ct, nb_oargs, nb_iargs); } +} - for (TCGOpcode op = 0; op < NB_OPS; op++) { - TCGOpDef *def = &tcg_op_defs[op]; - const TCGConstraintSet *tdefs; - TCGConstraintSetIndex con_set; - int nb_args; +static const TCGArgConstraint *opcode_args_ct(const TCGOp *op) +{ + TCGOpDef *def = &tcg_op_defs[op->opc]; + TCGConstraintSetIndex con_set; - nb_args = def->nb_iargs + def->nb_oargs; - if (nb_args == 0) { - continue; - } - - if (def->flags & TCG_OPF_NOT_PRESENT) { - def->args_ct = empty_cts; - continue; - } - - /* - * Macro magic should make it impossible, but double-check that - * the array index is in range. At the same time, double-check - * that the opcode is implemented, i.e. not C_NotImplemented. - */ - con_set = tcg_target_op_def(op); - tcg_debug_assert(con_set >= 0 && con_set < ARRAY_SIZE(constraint_sets)); - - /* The constraint arguments must match TCGOpcode arguments. */ - tdefs = &constraint_sets[con_set]; - tcg_debug_assert(tdefs->nb_oargs == def->nb_oargs); - tcg_debug_assert(tdefs->nb_iargs == def->nb_iargs); - - def->args_ct = all_cts[con_set]; + if (def->nb_iargs + def->nb_oargs == 0) { + return NULL; } + if (def->flags & TCG_OPF_NOT_PRESENT) { + return empty_cts; + } + + con_set = tcg_target_op_def(op->opc); + tcg_debug_assert(con_set >= 0 && con_set < ARRAY_SIZE(constraint_sets)); + + /* The constraint arguments must match TCGOpcode arguments. */ + tcg_debug_assert(constraint_sets[con_set].nb_oargs == def->nb_oargs); + tcg_debug_assert(constraint_sets[con_set].nb_iargs == def->nb_iargs); + + return all_cts[con_set]; } static void remove_label_use(TCGOp *op, int idx) @@ -3864,6 +3854,7 @@ liveness_pass_1(TCGContext *s) TCGTemp *ts; TCGOpcode opc = op->opc; const TCGOpDef *def = &tcg_op_defs[opc]; + const TCGArgConstraint *args_ct; switch (opc) { case INDEX_op_call: @@ -4153,8 +4144,9 @@ liveness_pass_1(TCGContext *s) break; default: + args_ct = opcode_args_ct(op); for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { - const TCGArgConstraint *ct = &def->args_ct[i]; + const TCGArgConstraint *ct = &args_ct[i]; TCGRegSet set, *pset; ts = arg_temp(op->args[i]); @@ -4941,6 +4933,7 @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op) { const TCGLifeData arg_life = op->life; TCGRegSet dup_out_regs, dup_in_regs; + const TCGArgConstraint *dup_args_ct; TCGTemp *its, *ots; TCGType itype, vtype; unsigned vece; @@ -4967,8 +4960,9 @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op) return; } - dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs; - dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].regs; + dup_args_ct = opcode_args_ct(op); + dup_out_regs = dup_args_ct[0].regs; + dup_in_regs = dup_args_ct[1].regs; /* Allocate the output register now. */ if (ots->val_type != TEMP_VAL_REG) { @@ -5054,6 +5048,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) int i, k, nb_iargs, nb_oargs; TCGReg reg; TCGArg arg; + const TCGArgConstraint *args_ct; const TCGArgConstraint *arg_ct; TCGTemp *ts; TCGArg new_args[TCG_MAX_OP_ARGS]; @@ -5098,6 +5093,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) break; } + args_ct = opcode_args_ct(op); + /* satisfy input constraints */ for (k = 0; k < nb_iargs; k++) { TCGRegSet i_preferred_regs, i_required_regs; @@ -5105,9 +5102,9 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) TCGTemp *ts2; int i1, i2; - i = def->args_ct[nb_oargs + k].sort_index; + i = args_ct[nb_oargs + k].sort_index; arg = op->args[i]; - arg_ct = &def->args_ct[i]; + arg_ct = &args_ct[i]; ts = arg_temp(arg); if (ts->val_type == TEMP_VAL_CONST @@ -5137,7 +5134,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) * register and move it. */ if (temp_readonly(ts) || !IS_DEAD_ARG(i) - || def->args_ct[arg_ct->alias_index].newreg) { + || args_ct[arg_ct->alias_index].newreg) { allocate_new_reg = true; } else if (ts->val_type == TEMP_VAL_REG) { /* @@ -5322,10 +5319,10 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) } /* satisfy the output constraints */ - for(k = 0; k < nb_oargs; k++) { - i = def->args_ct[k].sort_index; + for (k = 0; k < nb_oargs; k++) { + i = args_ct[k].sort_index; arg = op->args[i]; - arg_ct = &def->args_ct[i]; + arg_ct = &args_ct[i]; ts = arg_temp(arg); /* ENV should not be modified. */ @@ -5465,8 +5462,7 @@ static bool tcg_reg_alloc_dup2(TCGContext *s, const TCGOp *op) /* Allocate the output register now. */ if (ots->val_type != TEMP_VAL_REG) { TCGRegSet allocated_regs = s->reserved_regs; - TCGRegSet dup_out_regs = - tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs; + TCGRegSet dup_out_regs = opcode_args_ct(op)[0].regs; TCGReg oreg; /* Make sure to not spill the input registers. */