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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-437c74ace90sm30491535e9.16.2025.01.15.09.10.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 15 Jan 2025 09:10:24 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Ani Sinha , Igor Mammedov , Thomas Huth , Peter Maydell , Andrew Jones , qemu-arm@nongnu.org, Shannon Zhao , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 03/13] hw/arm/virt: Remove VirtMachineClass::disallow_affinity_adjustment Date: Wed, 15 Jan 2025 18:09:59 +0100 Message-ID: <20250115171009.19302-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250115171009.19302-1-philmd@linaro.org> References: <20250115171009.19302-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The VirtMachineClass::disallow_affinity_adjustment field was only used by virt-2.6 machine, which got removed. Remove it along with the GIC*_TARGETLIST_BITS definitions, and simplify virt_cpu_mp_affinity(). Signed-off-by: Philippe Mathieu-Daudé --- include/hw/arm/virt.h | 1 - include/hw/intc/arm_gic.h | 1 - include/hw/intc/arm_gicv3_common.h | 3 --- hw/arm/virt.c | 16 ---------------- 4 files changed, 21 deletions(-) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 27c5bb585cb..5d3b25509ff 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -117,7 +117,6 @@ typedef enum VirtGICType { struct VirtMachineClass { MachineClass parent; - bool disallow_affinity_adjustment; bool no_its; bool no_tcg_its; bool claim_edge_triggered_timers; diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h index 48f6a51a70a..f5e6e5e70b4 100644 --- a/include/hw/intc/arm_gic.h +++ b/include/hw/intc/arm_gic.h @@ -68,7 +68,6 @@ #include "qom/object.h" /* Number of SGI target-list bits */ -#define GIC_TARGETLIST_BITS 8 #define GIC_MAX_PRIORITY_BITS 8 #define GIC_MIN_PRIORITY_BITS 4 diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h index a3d6a0e5077..fff5e55a97d 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -45,9 +45,6 @@ #define GICV3_REDIST_SIZE 0x20000 #define GICV4_REDIST_SIZE 0x40000 -/* Number of SGI target-list bits */ -#define GICV3_TARGETLIST_BITS 16 - /* Maximum number of list registers (architectural limit) */ #define GICV3_LR_MAX 16 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 0080577e1a9..2a2a0bd9154 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1760,23 +1760,7 @@ void virt_machine_done(Notifier *notifier, void *data) static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) { uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; - VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); - if (!vmc->disallow_affinity_adjustment) { - /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the - * GIC's target-list limitations. 32-bit KVM hosts currently - * always create clusters of 4 CPUs, but that is expected to - * change when they gain support for gicv3. When KVM is enabled - * it will override the changes we make here, therefore our - * purposes are to make TCG consistent (with 64-bit KVM hosts) - * and to improve SGI efficiency. - */ - if (vms->gic_version == VIRT_GIC_VERSION_2) { - clustersz = GIC_TARGETLIST_BITS; - } else { - clustersz = GICV3_TARGETLIST_BITS; - } - } return arm_build_mp_affinity(idx, clustersz); }