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Tue, 14 Jan 2025 03:38:26 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c906009bsm618348266b.25.2025.01.14.03.38.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jan 2025 03:38:24 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 3AA985F938; Tue, 14 Jan 2025 11:38:22 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Stefan Weil , Pierrick Bouvier , Richard Henderson , =?utf-8?q?Alex_Benn=C3=A9?= =?utf-8?q?e?= Subject: [PATCH v2 05/37] semihosting/arm-compat: Include missing 'cpu.h' header Date: Tue, 14 Jan 2025 11:37:49 +0000 Message-Id: <20250114113821.768750-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250114113821.768750-1-alex.bennee@linaro.org> References: <20250114113821.768750-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé ARM semihosting implementations in "common-semi-target.h" must de-reference the target CPUArchState, which is declared in each target "cpu.h" header. Include it in order to avoid when refactoring: In file included from ../../semihosting/arm-compat-semi.c:169: ../target/riscv/common-semi-target.h:16:5: error: use of undeclared identifier 'RISCVCPU' 16 | RISCVCPU *cpu = RISCV_CPU(cs); | ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250103171037.11265-4-philmd@linaro.org> Signed-off-by: Alex Bennée --- semihosting/arm-compat-semi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c index d78c6428b9..86e5260e50 100644 --- a/semihosting/arm-compat-semi.c +++ b/semihosting/arm-compat-semi.c @@ -166,6 +166,7 @@ static LayoutInfo common_semi_find_bases(CPUState *cs) #endif +#include "cpu.h" #include "common-semi-target.h" /*