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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e2ddcb5bsm190228695e9.23.2025.01.13.11.56.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 11:56:32 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paul Burton , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen Subject: [PATCH v2 13/19] hw/mips/bootloader: Propagate CPU env to bl_gen_[d]li() Date: Mon, 13 Jan 2025 20:55:19 +0100 Message-ID: <20250113195525.57150-14-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113195525.57150-1-philmd@linaro.org> References: <20250113195525.57150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Propagate the target specific CPU env to the locally declared bl_gen_li() and bl_gen_dli() functions. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 198506431c5..464ed5f4f1a 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -213,7 +213,8 @@ static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset) } /* Pseudo instructions */ -static void bl_gen_li(void **p, bl_reg rt, uint32_t imm) +static void bl_gen_li(const CPUMIPSState *env, void **p, + bl_reg rt, uint32_t imm) { if (bootcpu_supports_isa(ISA_NANOMIPS32)) { bl_gen_lui_nm(p, rt, extract32(imm, 12, 20)); @@ -224,9 +225,10 @@ static void bl_gen_li(void **p, bl_reg rt, uint32_t imm) } } -static void bl_gen_dli(void **p, bl_reg rt, uint64_t imm) +static void bl_gen_dli(const CPUMIPSState *env, void **p, + bl_reg rt, uint64_t imm) { - bl_gen_li(p, rt, extract64(imm, 32, 32)); + bl_gen_li(env, p, rt, extract64(imm, 32, 32)); bl_gen_dsll(p, rt, rt, 16); bl_gen_ori(p, rt, rt, extract64(imm, 16, 16)); bl_gen_dsll(p, rt, rt, 16); @@ -237,9 +239,9 @@ static void bl_gen_load_ulong(const CPUMIPSState *env, void **p, bl_reg rt, target_ulong imm) { if (bootcpu_supports_isa(ISA_MIPS3)) { - bl_gen_dli(p, rt, imm); /* 64bit */ + bl_gen_dli(env, p, rt, imm); /* 64bit */ } else { - bl_gen_li(p, rt, imm); /* 32bit */ + bl_gen_li(env, p, rt, imm); /* 32bit */ } } @@ -301,7 +303,7 @@ void bl_gen_write_u32(const MIPSCPU *cpu, void **p, { const CPUMIPSState *env = &cpu->env; - bl_gen_li(p, BL_REG_K0, val); + bl_gen_li(env, p, BL_REG_K0, val); bl_gen_load_ulong(env, p, BL_REG_K1, addr); bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0); } @@ -311,7 +313,7 @@ void bl_gen_write_u64(const MIPSCPU *cpu, void **p, { const CPUMIPSState *env = &cpu->env; - bl_gen_dli(p, BL_REG_K0, val); + bl_gen_dli(env, p, BL_REG_K0, val); bl_gen_load_ulong(env, p, BL_REG_K1, addr); bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0); }