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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e9dc8826sm152686025e9.11.2025.01.13.11.56.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 11:56:27 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paul Burton , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen Subject: [PATCH v2 12/19] hw/mips/bootloader: Propagate CPU env to bl_gen_load_ulong() Date: Mon, 13 Jan 2025 20:55:18 +0100 Message-ID: <20250113195525.57150-13-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113195525.57150-1-philmd@linaro.org> References: <20250113195525.57150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Propagate the target specific CPU env to the locally declared bl_gen_load_ulong() function. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 33 ++++++++++++++++++++++----------- 1 file changed, 22 insertions(+), 11 deletions(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 9b074d9903b..198506431c5 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -233,7 +233,8 @@ static void bl_gen_dli(void **p, bl_reg rt, uint64_t imm) bl_gen_ori(p, rt, rt, extract64(imm, 0, 16)); } -static void bl_gen_load_ulong(void **p, bl_reg rt, target_ulong imm) +static void bl_gen_load_ulong(const CPUMIPSState *env, void **p, + bl_reg rt, target_ulong imm) { if (bootcpu_supports_isa(ISA_MIPS3)) { bl_gen_dli(p, rt, imm); /* 64bit */ @@ -245,7 +246,9 @@ static void bl_gen_load_ulong(void **p, bl_reg rt, target_ulong imm) /* Helpers */ void bl_gen_jump_to(const MIPSCPU *cpu, void **p, target_ulong jump_addr) { - bl_gen_load_ulong(p, BL_REG_T9, jump_addr); + const CPUMIPSState *env = &cpu->env; + + bl_gen_load_ulong(env, p, BL_REG_T9, jump_addr); bl_gen_jalr(p, BL_REG_T9); bl_gen_nop(p); /* delay slot */ } @@ -258,20 +261,22 @@ void bl_gen_jump_kernel(const MIPSCPU *cpu, void **p, bool set_a3, target_ulong a3, target_ulong kernel_addr) { + const CPUMIPSState *env = &cpu->env; + if (set_sp) { - bl_gen_load_ulong(p, BL_REG_SP, sp); + bl_gen_load_ulong(env, p, BL_REG_SP, sp); } if (set_a0) { - bl_gen_load_ulong(p, BL_REG_A0, a0); + bl_gen_load_ulong(env, p, BL_REG_A0, a0); } if (set_a1) { - bl_gen_load_ulong(p, BL_REG_A1, a1); + bl_gen_load_ulong(env, p, BL_REG_A1, a1); } if (set_a2) { - bl_gen_load_ulong(p, BL_REG_A2, a2); + bl_gen_load_ulong(env, p, BL_REG_A2, a2); } if (set_a3) { - bl_gen_load_ulong(p, BL_REG_A3, a3); + bl_gen_load_ulong(env, p, BL_REG_A3, a3); } bl_gen_jump_to(cpu, p, kernel_addr); @@ -280,8 +285,10 @@ void bl_gen_jump_kernel(const MIPSCPU *cpu, void **p, void bl_gen_write_ulong(const MIPSCPU *cpu, void **p, target_ulong addr, target_ulong val) { - bl_gen_load_ulong(p, BL_REG_K0, val); - bl_gen_load_ulong(p, BL_REG_K1, addr); + const CPUMIPSState *env = &cpu->env; + + bl_gen_load_ulong(env, p, BL_REG_K0, val); + bl_gen_load_ulong(env, p, BL_REG_K1, addr); if (bootcpu_supports_isa(ISA_MIPS3)) { bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0); } else { @@ -292,15 +299,19 @@ void bl_gen_write_ulong(const MIPSCPU *cpu, void **p, void bl_gen_write_u32(const MIPSCPU *cpu, void **p, target_ulong addr, uint32_t val) { + const CPUMIPSState *env = &cpu->env; + bl_gen_li(p, BL_REG_K0, val); - bl_gen_load_ulong(p, BL_REG_K1, addr); + bl_gen_load_ulong(env, p, BL_REG_K1, addr); bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0); } void bl_gen_write_u64(const MIPSCPU *cpu, void **p, target_ulong addr, uint64_t val) { + const CPUMIPSState *env = &cpu->env; + bl_gen_dli(p, BL_REG_K0, val); - bl_gen_load_ulong(p, BL_REG_K1, addr); + bl_gen_load_ulong(env, p, BL_REG_K1, addr); bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0); }