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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e4b8299sm10825477f8f.74.2025.01.12.16.48.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 12 Jan 2025 16:48:15 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Huacai Chen , Paul Burton , Aurelien Jarno , Jiaxun Yang Subject: [PATCH 04/23] hw/mips/bootloader: Propagate CPU env to bootcpu_supports_isa() Date: Mon, 13 Jan 2025 01:47:29 +0100 Message-ID: <20250113004748.41658-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113004748.41658-1-philmd@linaro.org> References: <20250113004748.41658-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Propagate the target specific CPU env to the locally declared bootcpu_supports_isa() function. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 1dd6ef20968..918ce7795c4 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -49,9 +49,9 @@ typedef enum bl_reg { BL_REG_RA = 31, } bl_reg; -static bool bootcpu_supports_isa(uint64_t isa_mask) +static bool bootcpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask) { - return cpu_supports_isa(&MIPS_CPU(first_cpu)->env, isa_mask); + return cpu_supports_isa(env, isa_mask); } static void st_nm32_p(void **ptr, uint32_t insn) @@ -69,7 +69,7 @@ static void st_nm32_p(void **ptr, uint32_t insn) /* Base types */ static void bl_gen_nop(void **ptr) { - if (bootcpu_supports_isa(ISA_NANOMIPS32)) { + if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_NANOMIPS32)) { st_nm32_p(ptr, 0x8000c000); } else { uint32_t *p = *ptr; @@ -120,7 +120,7 @@ static void bl_gen_i_type(void **ptr, uint8_t opcode, /* Single instructions */ static void bl_gen_dsll(void **p, bl_reg rd, bl_reg rt, uint8_t sa) { - if (bootcpu_supports_isa(ISA_MIPS3)) { + if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_MIPS3)) { bl_gen_r_type(p, 0, 0, rt, rd, sa, 0x38); } else { g_assert_not_reached(); /* unsupported */ @@ -129,7 +129,7 @@ static void bl_gen_dsll(void **p, bl_reg rd, bl_reg rt, uint8_t sa) static void bl_gen_jalr(void **p, bl_reg rs) { - if (bootcpu_supports_isa(ISA_NANOMIPS32)) { + if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_NANOMIPS32)) { uint32_t insn = 0; insn = deposit32(insn, 26, 6, 0b010010); /* JALRC */ @@ -196,7 +196,7 @@ static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8_t rs, uint16_t ofs12) static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset) { - if (bootcpu_supports_isa(ISA_NANOMIPS32)) { + if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_NANOMIPS32)) { bl_gen_sw_nm(p, rt, base, offset); } else { bl_gen_i_type(p, 0x2b, base, rt, offset); @@ -205,7 +205,7 @@ static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset) static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset) { - if (bootcpu_supports_isa(ISA_MIPS3)) { + if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_MIPS3)) { bl_gen_i_type(p, 0x3f, base, rt, offset); } else { g_assert_not_reached(); /* unsupported */ @@ -215,7 +215,7 @@ static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset) /* Pseudo instructions */ static void bl_gen_li(void **p, bl_reg rt, uint32_t imm) { - if (bootcpu_supports_isa(ISA_NANOMIPS32)) { + if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_NANOMIPS32)) { bl_gen_lui_nm(p, rt, extract32(imm, 12, 20)); bl_gen_ori_nm(p, rt, rt, extract32(imm, 0, 12)); } else { @@ -235,7 +235,7 @@ static void bl_gen_dli(void **p, bl_reg rt, uint64_t imm) static void bl_gen_load_ulong(void **p, bl_reg rt, target_ulong imm) { - if (bootcpu_supports_isa(ISA_MIPS3)) { + if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_MIPS3)) { bl_gen_dli(p, rt, imm); /* 64bit */ } else { bl_gen_li(p, rt, imm); /* 32bit */ @@ -281,7 +281,7 @@ void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val) { bl_gen_load_ulong(p, BL_REG_K0, val); bl_gen_load_ulong(p, BL_REG_K1, addr); - if (bootcpu_supports_isa(ISA_MIPS3)) { + if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_MIPS3)) { bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0); } else { bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0);