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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e2e8bea5sm160712395e9.31.2025.01.12.16.48.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 12 Jan 2025 16:48:09 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Huacai Chen , Paul Burton , Aurelien Jarno , Jiaxun Yang Subject: [PATCH 03/23] hw/mips/boston: Replace bl_gen_write_ulong() -> bl_gen_write_u64() Date: Mon, 13 Jan 2025 01:47:28 +0100 Message-ID: <20250113004748.41658-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113004748.41658-1-philmd@linaro.org> References: <20250113004748.41658-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "exec/hwaddr.h" defines: typedef uint64_t hwaddr; typedef struct MemMapEntry { hwaddr base; hwaddr size; } MemMapEntry; Since MemMapEntry::base is always of type uint64_t, we can directly use bl_gen_write_u64(). Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/boston.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 67044af962a..63dc654192a 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -329,20 +329,20 @@ static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr) /* Move CM GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS), - bl_gen_write_ulong(&p, regaddr, - boston_memmap[BOSTON_CM].base); + bl_gen_write_u64(&p, regaddr, + boston_memmap[BOSTON_CM].base); /* Move & enable GIC GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base + GCR_GIC_BASE_OFS), - bl_gen_write_ulong(&p, regaddr, - boston_memmap[BOSTON_GIC].base | GCR_GIC_BASE_GICEN_MSK); + bl_gen_write_u64(&p, regaddr, + boston_memmap[BOSTON_GIC].base | GCR_GIC_BASE_GICEN_MSK); /* Move & enable CPC GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base + GCR_CPC_BASE_OFS), - bl_gen_write_ulong(&p, regaddr, - boston_memmap[BOSTON_CPC].base | GCR_CPC_BASE_CPCEN_MSK); + bl_gen_write_u64(&p, regaddr, + boston_memmap[BOSTON_CPC].base | GCR_CPC_BASE_CPCEN_MSK); /* * Setup argument registers to follow the UHI boot protocol: