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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e38325esm10765264f8f.27.2025.01.12.16.49.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 12 Jan 2025 16:49:27 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Huacai Chen , Paul Burton , Aurelien Jarno , Jiaxun Yang Subject: [PATCH 17/23] hw/mips/bootloader: Propagate CPU to bl_gen_write_u64() Date: Mon, 13 Jan 2025 01:47:42 +0100 Message-ID: <20250113004748.41658-18-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113004748.41658-1-philmd@linaro.org> References: <20250113004748.41658-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Propagate the target agnostic CPU pointer to the publicly declared bl_gen_write_u64() function. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/mips/bootloader.h | 3 ++- hw/mips/bootloader.c | 9 +++++---- hw/mips/boston.c | 6 +++--- 3 files changed, 10 insertions(+), 8 deletions(-) diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h index cc2ffe3ab2c..946580f6f5c 100644 --- a/include/hw/mips/bootloader.h +++ b/include/hw/mips/bootloader.h @@ -24,6 +24,7 @@ void bl_gen_write_ulong(const MIPSCPU *cpu, void **ptr, target_ulong addr, target_ulong val); void bl_gen_write_u32(const MIPSCPU *cpu, void **ptr, target_ulong addr, uint32_t val); -void bl_gen_write_u64(void **ptr, target_ulong addr, uint64_t val); +void bl_gen_write_u64(const MIPSCPU *cpu, void **ptr, + target_ulong addr, uint64_t val); #endif diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 6f0222faf48..c5bad03b528 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -303,9 +303,10 @@ void bl_gen_write_u32(const MIPSCPU *cpu, void **p, bl_gen_sw(&cpu->env, p, BL_REG_K0, BL_REG_K1, 0x0); } -void bl_gen_write_u64(void **p, target_ulong addr, uint64_t val) +void bl_gen_write_u64(const MIPSCPU *cpu, void **p, + target_ulong addr, uint64_t val) { - bl_gen_dli(&MIPS_CPU(first_cpu)->env, p, BL_REG_K0, val); - bl_gen_load_ulong(&MIPS_CPU(first_cpu)->env, p, BL_REG_K1, addr); - bl_gen_sd(&MIPS_CPU(first_cpu)->env, p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_dli(&cpu->env, p, BL_REG_K0, val); + bl_gen_load_ulong(&cpu->env, p, BL_REG_K1, addr); + bl_gen_sd(&cpu->env, p, BL_REG_K0, BL_REG_K1, 0x0); } diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 3a06b776fe8..09c4dfade12 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -329,19 +329,19 @@ static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr) /* Move CM GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS), - bl_gen_write_u64(&p, regaddr, + bl_gen_write_u64(MIPS_CPU(first_cpu), &p, regaddr, boston_memmap[BOSTON_CM].base); /* Move & enable GIC GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base + GCR_GIC_BASE_OFS), - bl_gen_write_u64(&p, regaddr, + bl_gen_write_u64(MIPS_CPU(first_cpu), &p, regaddr, boston_memmap[BOSTON_GIC].base | GCR_GIC_BASE_GICEN_MSK); /* Move & enable CPC GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base + GCR_CPC_BASE_OFS), - bl_gen_write_u64(&p, regaddr, + bl_gen_write_u64(MIPS_CPU(first_cpu), &p, regaddr, boston_memmap[BOSTON_CPC].base | GCR_CPC_BASE_CPCEN_MSK); /*