diff mbox series

[15/23] hw/mips/bootloader: Propagate CPU to bl_gen_write_ulong()

Message ID 20250113004748.41658-16-philmd@linaro.org
State New
Headers show
Series hw/mips: Remove all uses of &first_cpu | expand

Commit Message

Philippe Mathieu-Daudé Jan. 13, 2025, 12:47 a.m. UTC 
Propagate the target agnostic CPU pointer to the publicly
declared bl_gen_write_ulong() function.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/hw/mips/bootloader.h |  3 ++-
 hw/mips/bootloader.c         | 13 +++++++------
 2 files changed, 9 insertions(+), 7 deletions(-)
diff mbox series

Patch

diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h
index 6b58eafb8bc..a7f174e16bc 100644
--- a/include/hw/mips/bootloader.h
+++ b/include/hw/mips/bootloader.h
@@ -20,7 +20,8 @@  void bl_gen_jump_kernel(const MIPSCPU *cpu, void **ptr,
                         bool set_a2, target_ulong a2,
                         bool set_a3, target_ulong a3,
                         target_ulong kernel_addr);
-void bl_gen_write_ulong(void **ptr, target_ulong addr, target_ulong val);
+void bl_gen_write_ulong(const MIPSCPU *cpu, void **ptr,
+                        target_ulong addr, target_ulong val);
 void bl_gen_write_u32(void **ptr, target_ulong addr, uint32_t val);
 void bl_gen_write_u64(void **ptr, target_ulong addr, uint64_t val);
 
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 9804051ab2d..c4fd85b9f42 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -283,14 +283,15 @@  void bl_gen_jump_kernel(const MIPSCPU *cpu, void **p,
     bl_gen_jump_to(cpu, p, kernel_addr);
 }
 
-void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val)
+void bl_gen_write_ulong(const MIPSCPU *cpu, void **p,
+                        target_ulong addr, target_ulong val)
 {
-    bl_gen_load_ulong(&MIPS_CPU(first_cpu)->env, p, BL_REG_K0, val);
-    bl_gen_load_ulong(&MIPS_CPU(first_cpu)->env, p, BL_REG_K1, addr);
-    if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_MIPS3)) {
-        bl_gen_sd(&MIPS_CPU(first_cpu)->env, p, BL_REG_K0, BL_REG_K1, 0x0);
+    bl_gen_load_ulong(&cpu->env, p, BL_REG_K0, val);
+    bl_gen_load_ulong(&cpu->env, p, BL_REG_K1, addr);
+    if (bootcpu_supports_isa(&cpu->env, ISA_MIPS3)) {
+        bl_gen_sd(&cpu->env, p, BL_REG_K0, BL_REG_K1, 0x0);
     } else {
-        bl_gen_sw(&MIPS_CPU(first_cpu)->env, p, BL_REG_K0, BL_REG_K1, 0x0);
+        bl_gen_sw(&cpu->env, p, BL_REG_K0, BL_REG_K1, 0x0);
     }
 }