From patchwork Sun Jan 12 22:16:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 856798 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1179441wrc; Sun, 12 Jan 2025 14:24:00 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWPm26fNDN67GUJHMrb0KKI1E6VZunBhaVvFaU6ZiFGu8ReLiIZ1wUPhzLbdweMYHFBvHHKTA==@linaro.org X-Google-Smtp-Source: AGHT+IFr+kyS/w1O5m6Q6dTWaHqmcdQWKPPWnwwlNsBNwZv4s+lbsmHt+RbLBLl8bPOhvOQL0QhO X-Received: by 2002:a05:620a:4456:b0:7b1:4f5c:6e86 with SMTP id af79cd13be357-7bcd973cff2mr2779988885a.17.1736720640166; Sun, 12 Jan 2025 14:24:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736720640; cv=none; d=google.com; s=arc-20240605; b=fRyHg8F4d4wArO/q0rQDDiqwYoTKt50WXvo72F7I/8E4jMHvr0aMvwF5OZrG0XWrD5 MMzhsTXVtgjzXAeZhx/HMXHfjNF25HDZKtlF/IlttXG5BhW8Arhd3mGhd0tlbmtiLFSm 1Zkvw+MnOOEwf4bS59ZJ3Hb1AxFEesYrZY1ywTlt3yIrme0KOU2lI5Ij8Eg7Tf8tsDVZ tpecnuhzCkLBE9lgM5EjJGD3ZbKL8EzrAbKqe0V/f1WJykhnraT8d4sLzCyA0X5mW1o7 U/7JLB3gxAKjzxLQINbRuKNo0XLGcxetuAXCMW44nBmnyElO72iU3M1KKty1Irmktd20 zYEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=SFoahiPSgH64KUxCBuOvqcnFDOzpDhwSVqu05ihWUQw=; fh=lA8KdGRRCLcXxei5dR52XWsTSutqQE1F1yBegzCCPPE=; b=T4gufUFaTebE42XoN7MJ+o9z8AppHzNdbSn2lP5QyWe6H8dNz06NaPRNijs5Z1DRDW WbU90iR3+VgFv8nE38QduugrkRqELoK4DdZS38CemPqn7LiwL6PS9mrgQkYZptZvZfxs 2R/ixf32r/BuCMphAruqTmEqFhL1tmoF05vSws0CSKEUwAnYmUCTHQkrtcggYwiWkgc/ 2U3TgHk/RjVHXor8pWiD6BJXsImVt3Ruj4ATggw/OMOWK3VGA3OExSc81eib5lCYt07N Q2z5d1FSn2xq1Vno5CsyCkmBYU7fNsGf8F4suMRXfDJ9PwPJHu6+TLxiiVC6evgLYjcz VtGA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="cm1+Z/RD"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7bce34fceffsi1027890985a.417.2025.01.12.14.23.59 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sun, 12 Jan 2025 14:24:00 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="cm1+Z/RD"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tX6IY-0000qL-PI; Sun, 12 Jan 2025 17:19:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tX6IO-0000fX-NH for qemu-devel@nongnu.org; Sun, 12 Jan 2025 17:19:01 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tX6IK-0006Ty-7R for qemu-devel@nongnu.org; Sun, 12 Jan 2025 17:18:59 -0500 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-4361b0ec57aso36065515e9.0 for ; Sun, 12 Jan 2025 14:18:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1736720334; x=1737325134; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SFoahiPSgH64KUxCBuOvqcnFDOzpDhwSVqu05ihWUQw=; b=cm1+Z/RDJdSQdCAxa8iZDvgsuMkA8PSC9bs+O78ftPn3c4NlYFF0Wzpu2A7Yzsp2bZ Lt6LXzT+bj28dJWO/gydvCViFkKYdybwZynFIxo8Gc0njKz+JvDmKrMPxoLaVVpnlK/5 xa9mHVUwTlvBvRST+w7sSUfdH5Q/mZsjFkP68VN3pYwZhP+uZMQczpmjMvewcLjHtwC1 UD9mhpFFjy/Qa0bqCsTkuxWGZR+JqB01DeiXINDok47ycTaXzEcqlwnsTrdb+TQxH1rC pwOMlwLlwQEn6JXh/xkiikkjrdGIa4jOlvVqYjbOLaGZmPMUJsBy+8QjTZbPJV1ErN8U f3pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736720334; x=1737325134; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SFoahiPSgH64KUxCBuOvqcnFDOzpDhwSVqu05ihWUQw=; b=s1oDwhwXaVyD7zPAAImkkyCTHOr/7/Zb6qSzf0D71MEaafsAuZMsmpA6CH9dTYOrYF ZAvlzJDwNcwLwulFBfkPSQ4JawnI0CmRd9y38mSJsSVV2QepdKyqHTthc/x/nF9m21/b O6I5gan66Wk0WUy0PiX1JRpZ2Iy6cW2zGmueS5vmkSMjPk4BJwHzHQYDkJb2my8gSKY6 e3GQQFDHxg8dxg7HOhwwP3v1R1mqPRvvoQsQJI48vIk1OB6jxiYz/jnjMaajbFcbz7Av 5FzdSn21m8Ufi+iCdFMJJfNiNkxvOOQXPM6p06PtlXUMnbGaEq2fqu2pTE2rDwrHOSCy I6BQ== X-Gm-Message-State: AOJu0Yw0Ohjp9ya2E2GgEPmyKsWkXHQFCtUNZXImJvy9S+opU/AaH0Ux wDzFAbJ1rSdHbyveJaJ1Np5enYxUouVI172VVmHQvJ89KhzvWa5mKWQu/5CuHstBgMXXrAAVhV6 oPcg= X-Gm-Gg: ASbGncuuY/U8ZFvKtB1BUbwwuCRUNy6+2GKb5NcWmC+xz8gjCyL0ZUoi8uiWaD3/LrL Os71vyqP2Qq+y2/rQNvXAPyvIvKxABHEdkC4PyfESrpLqcB9PXr38fyS5ImRiMPw2AZCW7s8n5n 7+jBFnf8SpZuj6tYO1MRQCSPKfQeJQR5mEMHzdQrnLYkGYvi4QrQccIGY9zFVf1hi/G2mJAhPfQ zbS00qiQ00O2QFGbsBJI0cPSlBibodlmNT/Jt6un2/4qldle1IGzgMM60lrg+tjIkXNE/G5IlpH aDKqSWF+c3AlFP5byMbFI96g/tE2qbM= X-Received: by 2002:a05:600c:4745:b0:434:9c60:95a3 with SMTP id 5b1f17b1804b1-436e26c4218mr180634545e9.11.1736720334426; Sun, 12 Jan 2025 14:18:54 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e2dc08bbsm156785245e9.12.2025.01.12.14.18.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 12 Jan 2025 14:18:53 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Edgar E. Iglesias" Subject: [PULL 17/49] hw/net/xilinx_ethlite: Map TX_CTRL as MMIO Date: Sun, 12 Jan 2025 23:16:53 +0100 Message-ID: <20250112221726.30206-18-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250112221726.30206-1-philmd@linaro.org> References: <20250112221726.30206-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add TX_CTRL to the TX registers MMIO region. The memory flat view becomes: (qemu) info mtree -f FlatView #0 Root memory region: system 0000000081000000-00000000810007e3 (prio 0, i/o): xlnx.xps-ethernetlite 00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio 00000000810007f4-00000000810007ff (prio 0, i/o): ethlite.tx[0]io 0000000081000800-0000000081000ff3 (prio 0, i/o): xlnx.xps-ethernetlite @0000000000000800 0000000081000ff4-0000000081000fff (prio 0, i/o): ethlite.tx[1]io 0000000081001000-00000000810017fb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000001000 00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io 0000000081001800-0000000081001ffb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000001800 0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias Message-Id: <20241112181044.92193-19-philmd@linaro.org> --- hw/net/xilinx_ethlite.c | 54 ++++++++++++++++++----------------------- 1 file changed, 24 insertions(+), 30 deletions(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 898c09b3981..5ab8ae43b2b 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -42,10 +42,8 @@ #define BUFSZ_MAX 0x07e4 #define A_MDIO_BASE 0x07e4 #define A_TX_BASE0 0x07f4 -#define R_TX_CTRL0 (0x07fc / 4) #define R_TX_BUF1 (0x0800 / 4) #define A_TX_BASE1 0x0ff4 -#define R_TX_CTRL1 (0x0ffc / 4) #define R_RX_BUF0 (0x1000 / 4) #define A_RX_BASE0 0x17fc @@ -56,6 +54,7 @@ enum { TX_LEN = 0, TX_GIE = 1, + TX_CTRL = 2, TX_MAX }; @@ -144,6 +143,9 @@ static uint64_t port_tx_read(void *opaque, hwaddr addr, unsigned int size) case TX_GIE: r = s->port[port_index].reg.tx_gie; break; + case TX_CTRL: + r = s->port[port_index].reg.tx_ctrl; + break; default: g_assert_not_reached(); } @@ -164,6 +166,26 @@ static void port_tx_write(void *opaque, hwaddr addr, uint64_t value, case TX_GIE: s->port[port_index].reg.tx_gie = value; break; + case TX_CTRL: + if ((value & (CTRL_P | CTRL_S)) == CTRL_S) { + qemu_send_packet(qemu_get_queue(s->nic), + txbuf_ptr(s, port_index), + s->port[port_index].reg.tx_len); + if (s->port[port_index].reg.tx_ctrl & CTRL_I) { + eth_pulse_irq(s); + } + } else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) { + memcpy(&s->conf.macaddr.a[0], txbuf_ptr(s, port_index), 6); + if (s->port[port_index].reg.tx_ctrl & CTRL_I) { + eth_pulse_irq(s); + } + } + /* + * We are fast and get ready pretty much immediately + * so we actually never flip the S nor P bits to one. + */ + s->port[port_index].reg.tx_ctrl = value & ~(CTRL_P | CTRL_S); + break; default: g_assert_not_reached(); } @@ -236,18 +258,12 @@ static uint64_t eth_read(void *opaque, hwaddr addr, unsigned int size) { XlnxXpsEthLite *s = opaque; - unsigned port_index = addr_to_port_index(addr); uint32_t r = 0; addr >>= 2; switch (addr) { - case R_TX_CTRL1: - case R_TX_CTRL0: - r = s->port[port_index].reg.tx_ctrl; - break; - default: r = tswap32(s->regs[addr]); break; @@ -260,33 +276,11 @@ eth_write(void *opaque, hwaddr addr, uint64_t val64, unsigned int size) { XlnxXpsEthLite *s = opaque; - unsigned int port_index = addr_to_port_index(addr); uint32_t value = val64; addr >>= 2; switch (addr) { - case R_TX_CTRL0: - case R_TX_CTRL1: - if ((value & (CTRL_P | CTRL_S)) == CTRL_S) { - qemu_send_packet(qemu_get_queue(s->nic), - txbuf_ptr(s, port_index), - s->port[port_index].reg.tx_len); - if (s->port[port_index].reg.tx_ctrl & CTRL_I) { - eth_pulse_irq(s); - } - } else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) { - memcpy(&s->conf.macaddr.a[0], txbuf_ptr(s, port_index), 6); - if (s->port[port_index].reg.tx_ctrl & CTRL_I) { - eth_pulse_irq(s); - } - } - - /* We are fast and get ready pretty much immediately so - we actually never flip the S nor P bits to one. */ - s->port[port_index].reg.tx_ctrl = value & ~(CTRL_P | CTRL_S); - break; - default: s->regs[addr] = tswap32(value); break;