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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e383654sm5134100f8f.30.2025.01.10.09.32.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 10 Jan 2025 09:32:28 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Gustavo Romero , qemu-ppc@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 2/2] hw/ppc/prep_systemio: Set IOMap IRQ in ResetExit() handler Date: Fri, 10 Jan 2025 18:32:17 +0100 Message-ID: <20250110173217.80942-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250110173217.80942-1-philmd@linaro.org> References: <20250110173217.80942-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since the IOMap output IRQ is created in prep_systemio_realize(), it can not yet be wired before the device is realized, thus it is not reset properly. Fix by moving the qemu_set_irq() call in the ResetExit handler. Signed-off-by: Philippe Mathieu-Daudé --- hw/ppc/prep_systemio.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/hw/ppc/prep_systemio.c b/hw/ppc/prep_systemio.c index 7cbf7e4eecd..87f412891e2 100644 --- a/hw/ppc/prep_systemio.c +++ b/hw/ppc/prep_systemio.c @@ -260,8 +260,6 @@ static void prep_systemio_realize(DeviceState *dev, Error **errp) qdev_init_gpio_out(dev, &s->non_contiguous_io_map_irq, 1); s->iomap_type = PORT0850_IOMAP_NONCONTIGUOUS; - qemu_set_irq(s->non_contiguous_io_map_irq, - s->iomap_type & PORT0850_IOMAP_NONCONTIGUOUS); s->softreset_irq = qdev_get_gpio_in(DEVICE(s->cpu), PPC6xx_INPUT_HRESET); isa_register_portio_list(isa, &s->portio, 0x0, ppc_io800_port_list, s, @@ -273,6 +271,14 @@ static void prep_systemio_realize(DeviceState *dev, Error **errp) &s->ppc_parity_mem); } +static void prep_systemio_reset_exit(Object *obj, ResetType type) +{ + PrepSystemIoState *s = PREP_SYSTEMIO(obj); + + qemu_set_irq(s->non_contiguous_io_map_irq, + s->iomap_type & PORT0850_IOMAP_NONCONTIGUOUS); +} + static const VMStateDescription vmstate_prep_systemio = { .name = "prep_systemio", .version_id = 1, @@ -295,10 +301,12 @@ static const Property prep_systemio_properties[] = { static void prep_systemio_class_initfn(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); dc->realize = prep_systemio_realize; dc->vmsd = &vmstate_prep_systemio; device_class_set_props(dc, prep_systemio_properties); + rc->phases.exit = prep_systemio_reset_exit; } static const TypeInfo prep_systemio800_info = {