From patchwork Fri Jan 10 16:02:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 856258 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp302638wrc; Fri, 10 Jan 2025 08:04:33 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXnp6CZN2XSk/BWZqjZwrn8NWnlXQ1gV2pg3D1UExOVGod+qDLrGaxYzzZL4F9S1mpMruIYWA==@linaro.org X-Google-Smtp-Source: AGHT+IHVYsj95SDoJvMqVmoxmF9VP/9pOtobFnPO9OPWmwdQCg3FoUoR8XPA97l+YsnlSbuxh15i X-Received: by 2002:a05:6122:30a9:b0:516:2d4e:4493 with SMTP id 71dfb90a1353d-51c6c43aafemr9853123e0c.1.1736525073457; Fri, 10 Jan 2025 08:04:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736525073; cv=none; d=google.com; s=arc-20240605; b=fLWplW5OZlrNcpIa8tp+BOwlnsDjHqOPMVzKuLIXRXRGy3StnH2z9EazwOMHysJOrs D+Chcv1sq8BssjIsUTibVRAVjks2yTrWRV/ZPlG8S0pOe1oRAj3UVUoubnSK0rvKApYG P3fNwyVn3MoqaTxC1yFNg78XUIlkEjDt+A18BaNO2iCqtKiw3x4J7GlLrWta9ym7oebM Mn1AFc6GsQxCUIox2X36vgDmibP7ZRhLY6figX7J45qF6aY9C9DxBdt1f73yFPuzRBnp pH8LHM5aK1D0doTY2yg9P/2R+xfBBLZCsDFUuevK2IK5Byc1vR/+1O0eB+vas2QCDSGG pyVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=jNENegiBgeAyoUJg+Zncnjnk99h1QRf7b0Ia8CM8ZQ4=; fh=Uq4CCH4qgIScoA1ZlzK6h1LD8Rw6xac8JtYTs6G5zlc=; b=KnmmnaVsHbwQidKI64EdFfszEPBSpqf3I/cuiV6qQUhcog+3GbUU9cxpYBNeEjCKiI ynV92HLOaVd53wgNF8mwfLHhFdVmyuHpwCzXvY/a5EblVCsm00ERKxEI9FXlGmp2wFPI HPZnFDmivMFWzAAPXF502tKXh+Nam/H1CG2TGXcNUuSLO8ktWumhgWVtyd8GL+sP8xBJ 6JMlpnyP1d9j82AgGKrmAxme/OCycXyEg8oI1/tEb3VegnMzTpvN+ta4gtn9lbmUKARu 7HOIHQL9ZVTrH7NIAPP1+8TAd2KhE1rtn6zQYgNPmlkokDf4z32/gIzAtNtzho6vmbE0 woyg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SQQ7wfyl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 71dfb90a1353d-51c7fd82f3dsi1732375e0c.163.2025.01.10.08.04.33 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 10 Jan 2025 08:04:33 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SQQ7wfyl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tWHTo-0007hD-Ox; Fri, 10 Jan 2025 11:03:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tWHTM-0007O4-DW for qemu-devel@nongnu.org; Fri, 10 Jan 2025 11:02:58 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tWHTG-0004Jp-4f for qemu-devel@nongnu.org; Fri, 10 Jan 2025 11:02:53 -0500 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-4362f61757fso22097255e9.2 for ; Fri, 10 Jan 2025 08:02:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1736524967; x=1737129767; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jNENegiBgeAyoUJg+Zncnjnk99h1QRf7b0Ia8CM8ZQ4=; b=SQQ7wfylJnaz8sjkErBRn+ygz+rmuOFXhr6fy+JbqyS8zeWz3M1DlmnS5gAFydfMbl 5aMBmQlMEMk9g9LTSHX6q6Y0KiADMGSEnZkrqE4rcbBb/EQdtvjsLWJnK7tKjS5QRLlP yzGw8ol8MjdK+LW5QtNUcZ2DXmojs4RmKhgp8jLomUivbEOu/W+PDBSfQuUPFl5YN88s D6t0qwiEjKvdswK0zDLFQUioH45oJPrimc9lw+ybJoD3abDe5/wQ8xES9y6cFsxpD/of 1QhMlp9u5AboWlpPuTw+v7zQCkfsGTfLNqLGK44U4Il9PcphceP3TkV4C7FwPtkI6k7K Pxig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736524967; x=1737129767; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jNENegiBgeAyoUJg+Zncnjnk99h1QRf7b0Ia8CM8ZQ4=; b=sIERS+zjv0cgwRL+t0SuXRG7wWhxrzV1lZVhjgocW8xl9R6XHk5BBWAReQQ71XU2UR jK/UzXu1x+C89dMaIXv1sdQat4z35xtp7HHrWBCFvRyRaZ5+Q2qvVVkecFORyh8LAq/7 kdcbE0+QOMVT0h3uuU7DCAv9pIdpDCL+O2Y788u9Yu2nmCOQolxRxDPiKbTQgrL43Dai Cx2EF8m5Fkxkhf/MEody4vIe04NKKYbrF67SOq3HLGXlE8WZ+5UPAF8JfNTqtgMiVtZT fLaqvsHQNx7urFIycqOZQcnrh5CKyYHI3UwP23SnPD0Naj5isYgxY2IUmZGu/qLaDNvR 6e6g== X-Gm-Message-State: AOJu0YwcZ7d1u28dmvCSp8e9HJn8cDvgmlG3yRPTsVJXmQgc0WGdfPON SDyzy4Fag4XvPPaYL3V/ESHHPuBeGic+8cULUM40K6o5QhqkPn7zfnTC14Fox2jQvR34suB4PeA xLns= X-Gm-Gg: ASbGncski94FT6W1AkJKbaHDtPzsGtIEO/IVav8SQxAIslJl4F+Dd1Vu/ftPwk5Uq4X VFWmG90RhBl5eHmINEJAI7C5BusgAPSHxtgEt2RSxmHUccuxzrNXNSopAcVhUSjQtZ12YHOkYjO FF/xO+cSM6fJpkkvljTUeQf2ZYGornUShjHGtGyZtKCScAC6OjWz46bLPoYy/0Zb/pR1N4cLmzv xSuAfETDL43KIOOJ9V04qt8XwAkswnNBarwkdHJLjmsGfR9Hmj05pd5fBU9aiwrRezwQ6KGCUmH GdZevG3kkgfvlm1Wy9fRWFNIezDlNHc= X-Received: by 2002:a05:600c:524f:b0:435:d22:9c9e with SMTP id 5b1f17b1804b1-436e26d0cf9mr98975045e9.19.1736524967313; Fri, 10 Jan 2025 08:02:47 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e2dc0babsm90587775e9.14.2025.01.10.08.02.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 10 Jan 2025 08:02:46 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 9/9] hw/arm/stellaris: Wire GPTM[#n] output to ADC input #n Date: Fri, 10 Jan 2025 17:02:04 +0100 Message-ID: <20250110160204.74997-10-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250110160204.74997-1-philmd@linaro.org> References: <20250110160204.74997-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The ADC model is very simple, and only consider the 4 GPTM IRQs as trigger. Currently they are all wired to the same input IRQ. This is a QDev design mistake. We could use a OR_IRQ, but the ADC actually really has one input for each GPTM, so have the ADC create 4 inputs and wire each GPTM output to them. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/stellaris.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index c89522332e2..446d6595a6d 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -701,8 +701,16 @@ static void stellaris_i2c_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); } -/* Analogue to Digital Converter. This is only partially implemented, - enough for applications that use a combined ADC and timer tick. */ +/* + * Analogue to Digital Converter. + * + * Each of the 4 trigger inputs has a MUX for 5 inputs + * (see Stellaris Data Sheet Figure 11-1: "ADC Module Block Diagram"). + * + * This model only consider the GPTM inputs, thus MUX is not implemented. + */ + +#define STELLARIS_ADC_TRIGGERS 4 #define STELLARIS_ADC_EM_CONTROLLER 0 #define STELLARIS_ADC_EM_COMP 1 @@ -986,7 +994,7 @@ static void stellaris_adc_init(Object *obj) memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, "adc", 0x1000); sysbus_init_mmio(sbd, &s->iomem); - qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); + qdev_init_gpio_in(dev, stellaris_adc_trigger, STELLARIS_ADC_TRIGGERS); } /* Board init. */ @@ -1061,7 +1069,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) DeviceState *gpio_dev[NUM_GPIO], *nvic; qemu_irq gpio_in[NUM_GPIO][8]; qemu_irq gpio_out[NUM_GPIO][8]; - qemu_irq adc; + DeviceState *adc; int sram_size; int flash_size; DeviceState *i2c_dev[NUM_I2C]; @@ -1144,15 +1152,12 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic, 28)); if (DEV_CAP(1, ADC)) { - dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, + adc = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, qdev_get_gpio_in(nvic, 14), qdev_get_gpio_in(nvic, 15), qdev_get_gpio_in(nvic, 16), qdev_get_gpio_in(nvic, 17), NULL); - adc = qdev_get_gpio_in(dev, 0); - } else { - adc = NULL; } for (i = 0; i < NUM_GPTM; i++) { if (DEV_CAP(2, GPTM(i))) { @@ -1166,9 +1171,12 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) sysbus_realize_and_unref(sbd, &error_fatal); sysbus_mmio_map(sbd, 0, 0x40030000 + i * 0x1000); sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, timer_irq[i])); + /* TODO: This is incorrect, but we get away with it because the ADC output is only ever pulsed. */ - qdev_connect_gpio_out(dev, 0, adc); + if (adc) { + qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(adc, i)); + } } }