From patchwork Thu Jan 2 18:06:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 854744 Delivered-To: patch@linaro.org Received: by 2002:a5d:4888:0:b0:385:e875:8a9e with SMTP id g8csp7909444wrq; Thu, 2 Jan 2025 10:28:30 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXoFIHcjLQbCy4N04g8rp2vSNnk6k1iTRjzCPNXPl9HahF7B5x1YO78RrHPlfSHIW2/Be4aHw==@linaro.org X-Google-Smtp-Source: AGHT+IGZktO0HHnUiaAtvgSNlMkYZa33q3KIRTq32x6rMTwHbi0mVQAtlOysYIDUR24VK1CPGeLn X-Received: by 2002:a05:6214:3111:b0:6d4:36ff:4358 with SMTP id 6a1803df08f44-6dd233571d8mr944768316d6.25.1735842510267; Thu, 02 Jan 2025 10:28:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1735842510; cv=none; d=google.com; s=arc-20240605; b=DqYRFpnB3TilNDkfnIa58iOAdiLtW8+kOqmNeykeYk3TLDGpB/pEzQWH1L2BZacd63 ZN5DM4pFp7x0dquZ/IzvLyVYXvQzmeyuflqfbIFVlIe9BG+EiQuql/n6XAt2JH2y6mL4 6OFFFAucf+htuHZr1ODCS6YqPBiGF/o5k+oUTypEPyngdKe74lF4gRR9r10unYrH70yi 4ZB6wyIgR8NAy3BlIIlKMti/QYobICy+8eumAKnwvmg/LMcfM2bg8X4Um3j1L/mmjQte 0O2OQoXxBynLAQpdGF2JpHLgVik9t7T0nmnPC/ENjfBbZ1JSBBBE0ez1o2AIfSaRpyav SE4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=fAaXJuliG4AX1JfPizZhxdX1L9P0mdLOxcA7EdEklLU=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=AqivZ5mFe5RPG9TJAKZpnHu/I6nGVy7ksZ6fbBJC7R/LVij7epnGi9NaNkdQS4I7v9 sWwNizgU9KVn9KbGCQvz6rUGAp9Tl8d7DdTrO5rus9qCEW5hFkakXCoB5ZQq2u1wnJ3Z WVrPzmNzxulJbEe2/vpizdN66lhto0wOI7XhxC4FVL4xzb2ikuQ5n7dPgfM4sbniIlum G+M8oBIXPnQqfHv6rfH9BwcnFRF/Y2gjMemyZUijzDWkT4U6rUC8w3zQqK06qUvQNvGg u+mSU1j5jV9QC+lPwZKxl9W84kSPk51wbqvIKJIqr6jRfJ8GtMyGO9MCbSQAl2OleRz5 UcCg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oSFYqxtv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 6a1803df08f44-6dd182532f1si341169056d6.370.2025.01.02.10.28.30 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 02 Jan 2025 10:28:30 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oSFYqxtv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tTPeu-000884-7g; Thu, 02 Jan 2025 13:11:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tTPeo-0007bX-V0 for qemu-devel@nongnu.org; Thu, 02 Jan 2025 13:10:55 -0500 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tTPel-0006IB-8Z for qemu-devel@nongnu.org; Thu, 02 Jan 2025 13:10:54 -0500 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-21649a7bcdcso154757725ad.1 for ; Thu, 02 Jan 2025 10:10:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1735841450; x=1736446250; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=fAaXJuliG4AX1JfPizZhxdX1L9P0mdLOxcA7EdEklLU=; b=oSFYqxtvPgcH+Pzz+KQCpuTRCa99zB5wKRu3wE0DScrIbER5rIlbKxRURgQCJIaj5Z lYI7ReGi44s6ebKFDwsFVqq7fl/WhZLe8ehGsy0wse4p1ukf1Dy6wwTfptiDMr4hB4V6 WBkD6HvjC/lt8Mk2Fnh3Lyb8IioGZexaz24uSL5kGA9qtU8jv2RhlMdXuxxFpbhYDgWA QmOCNLjTHfWT44bpfpU7oydEWwvP3eHJa9Y7Nlb5h18Bw+MeIR93VFmhG73O+Wvcijc/ I2Uoj+q/SEnOdGTOie8MLSvV9tuEZ7Y79ft4/BnicYRwMqCQIQq1qLZjpbxWK0ezDy30 RZKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735841450; x=1736446250; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fAaXJuliG4AX1JfPizZhxdX1L9P0mdLOxcA7EdEklLU=; b=Koi4UTFj6mF5eTZkbP17YGo8Hs6OwO9JI7fCP4p2VpXQPGVPtpmjz/VDoAtYGE1+So sZ11oOTVXzvg5UVr6dnHax5zBfTynMRApwxN1hnLeL1NpZHIgTVcSODrFMhvDZBhkTLd 9kSBxn2qVa6aXFOMEK1bjxPJzqEMEt9I97geHNcwo7tvCARGwjaTNOagkNLPoUiBfy89 zu/FHiTMCUm7137tK5ghWPV3mNfCsXIelQbX/y72tHHekzEfdPJ87JQFxqhK0Qe8wBXG BB6YeTJwZ9XOdYKrl90DtNqS/ky5b0wZ1EsktNoLpkbN3E0idqx/9K8WUdJg8Nd5nN0U u8nw== X-Gm-Message-State: AOJu0Yy0RoVw47cdVBH1W+zbV/zqN3IimVDEd4MEIKjKfd0Wk1GqlI72 zhnN6iRy/EAr/+A3nIePu7mb9coRLahN1bnsVjaCnE1eDMPv3Z8jvqU5qdnx9eJTYJRrO4KFq2E K X-Gm-Gg: ASbGncuwJ/RcncMJkq7YjMfJuP9scONCMMApCqYOUHKDmdnLLxj9yazBeuSbuC5+52Z XgfMatQ3PIpSzStMpKoZN4GxU1dkOvw7xLNGTM0Rfx6UfKyfjlN8fXeI0SdK44yvhXQLHpL1MHp 3/z5uXKir0ihh5BzhfP3ppqmPUkAd0IsMTwbmjWxiKReJoyfk6AJk8v6BjI16Is4+1ZMRFXB1xQ rfu6l8s9W3s4WVzKUWtrkEaFTShwQ77nlqyj9xkVHKgS+RCUI6BDqySJFmScg== X-Received: by 2002:a05:6a00:8087:b0:725:d1d5:6d80 with SMTP id d2e1a72fcca58-72abde65a85mr61592488b3a.7.1735841449962; Thu, 02 Jan 2025 10:10:49 -0800 (PST) Received: from stoup.. ([63.239.63.212]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72aad8dbaf1sm24620827b3a.112.2025.01.02.10.10.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jan 2025 10:10:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 70/73] tcg: Merge extract2 operations Date: Thu, 2 Jan 2025 10:06:50 -0800 Message-ID: <20250102180654.1420056-71-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250102180654.1420056-1-richard.henderson@linaro.org> References: <20250102180654.1420056-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 5 +---- tcg/optimize.c | 10 +++++----- tcg/tcg-op.c | 4 ++-- tcg/tcg.c | 6 ++---- target/i386/tcg/emit.c.inc | 12 +----------- tcg/aarch64/tcg-target.c.inc | 6 ++---- tcg/arm/tcg-target.c.inc | 4 ++-- tcg/i386/tcg-target.c.inc | 5 ++--- 8 files changed, 17 insertions(+), 35 deletions(-) diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index d390d639ee..c9069525a1 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -72,6 +72,7 @@ DEF(rotr, 1, 2, 0, TCG_OPF_INT) DEF(extract, 1, 1, 2, TCG_OPF_INT) DEF(sextract, 1, 1, 2, TCG_OPF_INT) DEF(deposit, 1, 2, 2, TCG_OPF_INT) +DEF(extract2, 1, 2, 1, TCG_OPF_INT) DEF(brcond, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | TCG_OPF_INT) DEF(setcond, 1, 2, 1, TCG_OPF_INT) @@ -81,8 +82,6 @@ DEF(movcond, 1, 4, 1, TCG_OPF_INT) /* load/store */ DEF(ld_i32, 1, 1, 2, 0) DEF(st_i32, 0, 2, 2, 0) -/* shifts/rotates */ -DEF(extract2_i32, 1, 2, 1, 0) DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH) DEF(setcond2_i32, 1, 4, 1, 0) @@ -96,8 +95,6 @@ DEF(ctpop_i32, 1, 1, 0, 0) /* load/store */ DEF(ld_i64, 1, 1, 2, 0) DEF(st_i64, 0, 2, 2, 0) -/* shifts/rotates */ -DEF(extract2_i64, 1, 2, 1, 0) /* size changing ops */ DEF(ext_i32_i64, 1, 1, 0, 0) diff --git a/tcg/optimize.c b/tcg/optimize.c index 25ab293a73..82606a00f5 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1831,12 +1831,12 @@ static bool fold_extract2(OptContext *ctx, TCGOp *op) uint64_t v2 = arg_info(op->args[2])->val; int shr = op->args[3]; - if (op->opc == INDEX_op_extract2_i64) { - v1 >>= shr; - v2 <<= 64 - shr; - } else { + if (op->type == TCG_TYPE_I32) { v1 = (uint32_t)v1 >> shr; v2 = (uint64_t)((int32_t)v2 << (32 - shr)); + } else { + v1 >>= shr; + v2 <<= 64 - shr; } return tcg_opt_gen_movi(ctx, op, op->args[0], v1 | v2); } @@ -2766,7 +2766,7 @@ void tcg_optimize(TCGContext *s) case INDEX_op_extract: done = fold_extract(&ctx, op); break; - CASE_OP_32_64(extract2): + case INDEX_op_extract2: done = fold_extract2(&ctx, op); break; case INDEX_op_ext_i32_i64: diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 65a6031eaf..f3f758b15b 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1070,7 +1070,7 @@ void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah, } else if (al == ah) { tcg_gen_rotri_i32(ret, al, ofs); } else if (TCG_TARGET_HAS_extract2(TCG_TYPE_I32)) { - tcg_gen_op4i_i32(INDEX_op_extract2_i32, ret, al, ah, ofs); + tcg_gen_op4i_i32(INDEX_op_extract2, ret, al, ah, ofs); } else { TCGv_i32 t0 = tcg_temp_ebb_new_i32(); tcg_gen_shri_i32(t0, al, ofs); @@ -2802,7 +2802,7 @@ void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, } else if (al == ah) { tcg_gen_rotri_i64(ret, al, ofs); } else if (TCG_TARGET_HAS_extract2(TCG_TYPE_I64)) { - tcg_gen_op4i_i64(INDEX_op_extract2_i64, ret, al, ah, ofs); + tcg_gen_op4i_i64(INDEX_op_extract2, ret, al, ah, ofs); } else { TCGv_i64 t0 = tcg_temp_ebb_new_i64(); tcg_gen_shri_i64(t0, al, ofs); diff --git a/tcg/tcg.c b/tcg/tcg.c index 77f28147a1..e8377a9bbe 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2224,6 +2224,8 @@ bool tcg_op_supported(TCGOpcode op, TCGType type) return has_type && TCG_TARGET_HAS_div2(type); case INDEX_op_eqv: return has_type && TCG_TARGET_HAS_eqv(type); + case INDEX_op_extract2: + return has_type && TCG_TARGET_HAS_extract2(type); case INDEX_op_muls2: return has_type && TCG_TARGET_HAS_muls2(type); case INDEX_op_mulsh: @@ -2251,8 +2253,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type) case INDEX_op_sub2: return has_type && TCG_TARGET_HAS_sub2(type); - case INDEX_op_extract2_i32: - return TCG_TARGET_HAS_extract2(TCG_TYPE_I32); case INDEX_op_bswap16_i32: case INDEX_op_bswap32_i32: return TCG_TARGET_HAS_bswap(TCG_TYPE_I32); @@ -2271,8 +2271,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type) case INDEX_op_extrh_i64_i32: return TCG_TARGET_REG_BITS == 64; - case INDEX_op_extract2_i64: - return TCG_TARGET_REG_BITS == 64 && TCG_TARGET_HAS_extract2(TCG_TYPE_I64); case INDEX_op_bswap16_i64: case INDEX_op_bswap32_i64: case INDEX_op_bswap64_i64: diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 00f7a6123a..c8fb3c36d9 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -19,16 +19,6 @@ * License along with this library; if not, see . */ -/* - * Sometimes, knowing what the backend has can produce better code. - * The exact opcode to check depends on 32- vs. 64-bit. - */ -#ifdef TARGET_X86_64 -#define INDEX_op_extract2_tl INDEX_op_extract2_i64 -#else -#define INDEX_op_extract2_tl INDEX_op_extract2_i32 -#endif - #define MMX_OFFSET(reg) \ ({ assert((reg) >= 0 && (reg) <= 7); \ offsetof(CPUX86State, fpregs[reg].mmx); }) @@ -2993,7 +2983,7 @@ static void gen_PMOVMSKB(DisasContext *s, X86DecodedInsn *decode) tcg_gen_ld8u_tl(s->T0, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec_len - 1))); while (vec_len > 8) { vec_len -= 8; - if (tcg_op_supported(INDEX_op_extract2_tl, TCG_TYPE_TL)) { + if (tcg_op_supported(INDEX_op_extract2, TCG_TYPE_TL)) { /* * Load the next byte of the result into the high byte of T. * TCG does a similar expansion of deposit to shl+extract2; by diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 57f4e05b5c..d982ac38a1 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2426,8 +2426,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext, tcg_out_sbfm(s, ext, a0, a1, a2, a2 + args[3] - 1); break; - case INDEX_op_extract2_i64: - case INDEX_op_extract2_i32: + case INDEX_op_extract2: tcg_out_extr(s, ext, a0, REG0(2), REG0(1), args[3]); break; @@ -2998,8 +2997,7 @@ static TCGConstraintSetIndex tcg_target_op_def(const TCGOp *op) case INDEX_op_deposit: return C_O1_I2(r, 0, rZ); - case INDEX_op_extract2_i32: - case INDEX_op_extract2_i64: + case INDEX_op_extract2: return C_O1_I2(r, rZ, rZ); case INDEX_op_add2: diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 1bf020ed67..ef33cf0ac7 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2133,7 +2133,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, case INDEX_op_sextract: tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]); break; - case INDEX_op_extract2_i32: + case INDEX_op_extract2: /* ??? These optimization vs zero should be generic. */ /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */ if (const_args[1]) { @@ -2229,7 +2229,7 @@ static TCGConstraintSetIndex tcg_target_op_def(const TCGOp *op) return C_O0_I2(r, rIN); case INDEX_op_deposit: return C_O1_I2(r, 0, rZ); - case INDEX_op_extract2_i32: + case INDEX_op_extract2: return C_O1_I2(r, rZ, rZ); case INDEX_op_movcond: return C_O1_I4(r, r, rIN, rIK, 0); diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 917775b7f6..61acf23708 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -3093,7 +3093,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, } break; - OP_32_64(extract2): + case INDEX_op_extract2: /* Note that SHRD outputs to the r/m operand. */ tcg_out_modrm(s, OPC_SHRD_Ib + rexw, a2, a0); tcg_out8(s, args[3]); @@ -3726,8 +3726,7 @@ static TCGConstraintSetIndex tcg_target_op_def(const TCGOp *op) case INDEX_op_ctpop_i64: return C_O1_I1(r, r); - case INDEX_op_extract2_i32: - case INDEX_op_extract2_i64: + case INDEX_op_extract2: return C_O1_I2(r, 0, r); case INDEX_op_deposit: