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([63.239.63.212]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72ad3393d5fsm20604456b3a.154.2025.01.02.10.07.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jan 2025 10:07:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 39/73] tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64 Date: Thu, 2 Jan 2025 10:06:19 -0800 Message-ID: <20250102180654.1420056-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250102180654.1420056-1-richard.henderson@linaro.org> References: <20250102180654.1420056-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Extracts which abut bit 32 may use 32-bit shifts. Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-has.h | 24 +++++++----------------- tcg/riscv/tcg-target.c.inc | 16 ++++++++++++---- 2 files changed, 19 insertions(+), 21 deletions(-) diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h index efebc46109..2caec10a18 100644 --- a/tcg/riscv/tcg-target-has.h +++ b/tcg/riscv/tcg-target-has.h @@ -84,31 +84,21 @@ static inline bool tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len) { - if (ofs == 0) { - switch (len) { - case 16: - return cpuinfo & CPUINFO_ZBB; - case 32: - return (cpuinfo & CPUINFO_ZBA) && type == TCG_TYPE_I64; - } + if (type == TCG_TYPE_I64 && ofs + len == 32) { + /* ofs > 0 uses SRLIW; ofs == 0 uses add.uw. */ + return ofs || (cpuinfo & CPUINFO_ZBA); } - return false; + return (cpuinfo & CPUINFO_ZBB) && ofs == 0 && len == 16; } #define TCG_TARGET_extract_valid tcg_target_extract_valid static inline bool tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len) { - if (ofs == 0) { - switch (len) { - case 8: - case 16: - return cpuinfo & CPUINFO_ZBB; - case 32: - return type == TCG_TYPE_I64; - } + if (type == TCG_TYPE_I64 && ofs + len == 32) { + return true; } - return false; + return (cpuinfo & CPUINFO_ZBB) && ofs == 0 && (len == 8 || len == 16); } #define TCG_TARGET_sextract_valid tcg_target_sextract_valid diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 8122187665..fb7cf0ca03 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -2344,8 +2344,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_extract_i64: - if (a2 == 0 && args[3] == 32) { - tcg_out_ext32u(s, a0, a1); + if (a2 + args[3] == 32) { + if (a2 == 0) { + tcg_out_ext32u(s, a0, a1); + } else { + tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2); + } break; } /* FALLTHRU */ @@ -2358,8 +2362,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_sextract_i64: - if (a2 == 0 && args[3] == 32) { - tcg_out_ext32s(s, a0, a1); + if (a2 + args[3] == 32) { + if (a2 == 0) { + tcg_out_ext32s(s, a0, a1); + } else { + tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2); + } break; } /* FALLTHRU */