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([63.239.63.212]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72ad3393d5fsm20604456b3a.154.2025.01.02.10.07.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jan 2025 10:07:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 16/73] tcg: Rename tcg-target.opc.h to tcg-target-opc.h.inc Date: Thu, 2 Jan 2025 10:05:56 -0800 Message-ID: <20250102180654.1420056-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250102180654.1420056-1-richard.henderson@linaro.org> References: <20250102180654.1420056-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In addition, add empty files for mips, sparc64 and tci. Make the include unconditional within tcg-opc.h. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- include/tcg/tcg-opc.h | 4 +--- tcg/aarch64/{tcg-target.opc.h => tcg-target-opc.h.inc} | 0 tcg/arm/{tcg-target.opc.h => tcg-target-opc.h.inc} | 0 tcg/i386/{tcg-target.opc.h => tcg-target-opc.h.inc} | 0 tcg/loongarch64/{tcg-target.opc.h => tcg-target-opc.h.inc} | 0 tcg/mips/tcg-target-opc.h.inc | 1 + tcg/ppc/{tcg-target.opc.h => tcg-target-opc.h.inc} | 0 tcg/riscv/{tcg-target.opc.h => tcg-target-opc.h.inc} | 0 tcg/s390x/{tcg-target.opc.h => tcg-target-opc.h.inc} | 0 tcg/sparc64/tcg-target-opc.h.inc | 1 + tcg/tci/tcg-target-opc.h.inc | 1 + 11 files changed, 4 insertions(+), 3 deletions(-) rename tcg/aarch64/{tcg-target.opc.h => tcg-target-opc.h.inc} (100%) rename tcg/arm/{tcg-target.opc.h => tcg-target-opc.h.inc} (100%) rename tcg/i386/{tcg-target.opc.h => tcg-target-opc.h.inc} (100%) rename tcg/loongarch64/{tcg-target.opc.h => tcg-target-opc.h.inc} (100%) create mode 100644 tcg/mips/tcg-target-opc.h.inc rename tcg/ppc/{tcg-target.opc.h => tcg-target-opc.h.inc} (100%) rename tcg/riscv/{tcg-target.opc.h => tcg-target-opc.h.inc} (100%) rename tcg/s390x/{tcg-target.opc.h => tcg-target-opc.h.inc} (100%) create mode 100644 tcg/sparc64/tcg-target-opc.h.inc create mode 100644 tcg/tci/tcg-target-opc.h.inc diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 546eb49c11..93622f3f6b 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -301,9 +301,7 @@ DEF(cmpsel_vec, 1, 4, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_cmpsel_vec)) DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT) -#if TCG_TARGET_MAYBE_vec -#include "tcg-target.opc.h" -#endif +#include "tcg-target-opc.h.inc" #ifdef TCG_TARGET_INTERPRETER /* These opcodes are only for use between the tci generator and interpreter. */ diff --git a/tcg/aarch64/tcg-target.opc.h b/tcg/aarch64/tcg-target-opc.h.inc similarity index 100% rename from tcg/aarch64/tcg-target.opc.h rename to tcg/aarch64/tcg-target-opc.h.inc diff --git a/tcg/arm/tcg-target.opc.h b/tcg/arm/tcg-target-opc.h.inc similarity index 100% rename from tcg/arm/tcg-target.opc.h rename to tcg/arm/tcg-target-opc.h.inc diff --git a/tcg/i386/tcg-target.opc.h b/tcg/i386/tcg-target-opc.h.inc similarity index 100% rename from tcg/i386/tcg-target.opc.h rename to tcg/i386/tcg-target-opc.h.inc diff --git a/tcg/loongarch64/tcg-target.opc.h b/tcg/loongarch64/tcg-target-opc.h.inc similarity index 100% rename from tcg/loongarch64/tcg-target.opc.h rename to tcg/loongarch64/tcg-target-opc.h.inc diff --git a/tcg/mips/tcg-target-opc.h.inc b/tcg/mips/tcg-target-opc.h.inc new file mode 100644 index 0000000000..84e777bfe5 --- /dev/null +++ b/tcg/mips/tcg-target-opc.h.inc @@ -0,0 +1 @@ +/* No target specific opcodes. */ diff --git a/tcg/ppc/tcg-target.opc.h b/tcg/ppc/tcg-target-opc.h.inc similarity index 100% rename from tcg/ppc/tcg-target.opc.h rename to tcg/ppc/tcg-target-opc.h.inc diff --git a/tcg/riscv/tcg-target.opc.h b/tcg/riscv/tcg-target-opc.h.inc similarity index 100% rename from tcg/riscv/tcg-target.opc.h rename to tcg/riscv/tcg-target-opc.h.inc diff --git a/tcg/s390x/tcg-target.opc.h b/tcg/s390x/tcg-target-opc.h.inc similarity index 100% rename from tcg/s390x/tcg-target.opc.h rename to tcg/s390x/tcg-target-opc.h.inc diff --git a/tcg/sparc64/tcg-target-opc.h.inc b/tcg/sparc64/tcg-target-opc.h.inc new file mode 100644 index 0000000000..84e777bfe5 --- /dev/null +++ b/tcg/sparc64/tcg-target-opc.h.inc @@ -0,0 +1 @@ +/* No target specific opcodes. */ diff --git a/tcg/tci/tcg-target-opc.h.inc b/tcg/tci/tcg-target-opc.h.inc new file mode 100644 index 0000000000..84e777bfe5 --- /dev/null +++ b/tcg/tci/tcg-target-opc.h.inc @@ -0,0 +1 @@ +/* No target specific opcodes. */