From patchwork Fri Dec 13 17:31:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 850174 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp1640518wry; Fri, 13 Dec 2024 09:39:09 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUKX3gKB1cz4Y/EznoE23hwJjn0K9QPdNWTXZDCRZnohk+usCslvfZonpsJC9aTu0hUB2/6Rw==@linaro.org X-Google-Smtp-Source: AGHT+IEHScMCHTf2ys6yo46tkDhHGfsQn6z6Zb8XGCshAIj9MxY2rTBXnJTYSc+1BIBWtBdDmXgU X-Received: by 2002:a17:906:6a08:b0:aa6:9e0f:d985 with SMTP id a640c23a62f3a-aab779c7673mr324261566b.35.1734111549182; Fri, 13 Dec 2024 09:39:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1734111549; cv=none; d=google.com; s=arc-20240605; b=dvslbC+ujghXN16bZTny4JUK3/6gTWYCPXo685zoXfxG4PiopNwGZ0QhbE7w9OY/KW /prXKC+03dSYqVBDtFmGqzxRIG/e4pfMT+l2tdCrpCaNifJS6phGL6oNw0qtApHbi5oN R2Wy429J1uvkR83ZjI+mKBCzM37uFmmfpaexHeUF4MaiHGREasE4wH55JBFZ5U7E4KEv Zre/KIrFBvO2OVm1njG+TConkMslcVp4iWXbWeW4QNy4Ot+th6iwzQLPMU7qMDPGLbqq y8bGh9dJnrWYAFYq23sR2e5uKhR5mN7MkXAeZbSEIF/YRwAXZhBWebOd19LnrBXD3q9s Krsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lGbtCRWoydk8pPXUYUd7BrLc4u+jFF25VA+zygABZmk=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=GqQ+OcObpWD5iC0CT0y5M5mXW8C0SH8VhcgnNIb4ZjKrwepaP/602lEEWCD8vy+79+ vpTg+nGCRV2ID1apDHP5PoCCT0Uh29F6T74htdfzy+lPQXXHlwcGUmKlhl247Qvuyb0W +ydP2vx00rPgBdSJQSO552MRnuD8qftDzm1k/ZJAfxdo97VAOfm7x9bsIH6LtCkpane9 ciP3d5t9PkGjxtiwfRocXNIJT/lhfLy6ad4LCES2iVKGt6u+5Davw0xjYIXcquvYHfYu ZEBrBmvWIL70siwUZtG3dSQoiEExbbDJzJLeiCzom0S/NrzUM8PQVV0dRryr11o3f4t5 h2VQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OM3Qsu6Z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a640c23a62f3a-aa6261d4843si1297281466b.786.2024.12.13.09.39.08 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 13 Dec 2024 09:39:09 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OM3Qsu6Z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tM9YL-0001TQ-HS; Fri, 13 Dec 2024 12:34:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tM9Xg-0007jc-P5 for qemu-devel@nongnu.org; Fri, 13 Dec 2024 12:33:32 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tM9Xd-0001eP-Rm for qemu-devel@nongnu.org; Fri, 13 Dec 2024 12:33:32 -0500 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-385e1fcb0e1so1096628f8f.2 for ; Fri, 13 Dec 2024 09:33:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1734111206; x=1734716006; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=lGbtCRWoydk8pPXUYUd7BrLc4u+jFF25VA+zygABZmk=; b=OM3Qsu6Z777ZbqmarPit+48k3ysrmx8Y5Vtwa5OoiWi0342Qse98JVMpdO0E6ijBI4 gK6AcnbYTaP4vO+eIGLMTNn45Vui/CI3RskTNp4uvfMsv8kq/ZTluLX0S+ovyVSFPrKa MlhISJyVlyanJLKsQkIy5dqvdKUP5BqjZ2D5qOaXRS4MoC/sxv0hKJOzWx24+choDbng jDgFCPp8DvYfP5E+2eFjrKjUgI+dXp4P5yzOLn4I3XqfqWzEYmLpXRHTJMiM6nVfV6q8 SnczAK3ArIybVkMkfIh5tKdwZwIV4u/YjsNJuek5d10fBwxkJyB5Eqs2ddtwvDmtOGmF BWkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734111206; x=1734716006; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lGbtCRWoydk8pPXUYUd7BrLc4u+jFF25VA+zygABZmk=; b=j6jVDit6Vrs5ykjuiLufL68l6qFr8oOAaUACRuNj3vrV1tiimUqYZL+Os1yQkZpTEZ W9as4d44Emlm9j1DNeKuDoAbFcDTYUCsVdU/tI5a87KMQel2c24y6qwDgY0TCUJEAfxS oShylN6F2h3mmFIByAz/jgwVlk3eeNuRF0jN+UpqoBVXugwxAv830zpELQ0Ui/lt4YPF 0bEo5EYrNMR9JnTZV7vRD21EdnLbZL31ltjon2yn2+2I3c+spePSg0JZk6fAc3+ZV57h oynNK8WkisEetCXk2djEBg7s64IMH2koKsK4ouGfTcADcxSA3XncVg+e+SjVmJ0dfgMd W8pw== X-Gm-Message-State: AOJu0YwcjjRgwPDFHc/q944q29OHYbXDLhBhatMpPBPF3pl07lM4sijt 4ui+DKcdoW7FtwkN7KPjmwfGQhJ4EgSBDMscXvPuAcYXnREhCyO3xO+DPZI2NvgpUo/q0yY/WTJ n X-Gm-Gg: ASbGnctA0tXNZs97Gtlxq2+ePwH4L0dKec16uKjGpC7Sz5bmv7ZkhQIEZf6tYd2PYpF 5EuUPI3Gz4KUdilZBqveagbfVqzosiIBhkz6ycj7v+jOrZXNnQqkfIPQJXYSDeZs/sM3ysqpb7n K3T/7QCAVJ+NdE+dDshgYmr9pIjWfoaoJ3lF9wjTHZ1zD6CdBzBvh2mADMjWo1LTFY4NCaa/lRT z9L2ufnW56PXRMIlFmZeCDf+ytk4aiI0u/yYwCkpoKOLBN1/9cSzZHPTeXT2g== X-Received: by 2002:a05:6000:2ad:b0:385:df6b:7ef6 with SMTP id ffacd0b85a97d-3888e0be442mr2454999f8f.51.1734111206322; Fri, 13 Dec 2024 09:33:26 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-388c80162ddsm87026f8f.37.2024.12.13.09.33.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Dec 2024 09:33:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 51/85] target/arm: Convert FCVTXN to decodetree Date: Fri, 13 Dec 2024 17:31:55 +0000 Message-Id: <20241213173229.3308926-52-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241213173229.3308926-1-peter.maydell@linaro.org> References: <20241213173229.3308926-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Remove handle_2misc_narrow as this was the last insn decoded by that function. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20241211163036.2297116-52-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/a64.decode | 4 ++ target/arm/tcg/translate-a64.c | 101 +++++++-------------------------- 2 files changed, 24 insertions(+), 81 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 456912cd7ca..d8902dfb226 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -74,6 +74,7 @@ @qrr_b . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=0 @qrr_h . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=1 +@qrr_s . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=2 @qrr_bh . q:1 ...... . esz:1 ...... ...... rn:5 rd:5 &qrr_e @qrr_hs . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=%esz_hs @qrr_e . q:1 ...... esz:2 ...... ...... rn:5 rd:5 &qrr_e @@ -1648,6 +1649,8 @@ SQXTUN_s 0111 1110 ..1 00001 00101 0 ..... ..... @rr_e SQXTN_s 0101 1110 ..1 00001 01001 0 ..... ..... @rr_e UQXTN_s 0111 1110 ..1 00001 01001 0 ..... ..... @rr_e +FCVTXN_s 0111 1110 011 00001 01101 0 ..... ..... @rr_s + # Advanced SIMD two-register miscellaneous SQABS_v 0.00 1110 ..1 00000 01111 0 ..... ..... @qrr_e @@ -1680,4 +1683,5 @@ SQXTN_v 0.00 1110 ..1 00001 01001 0 ..... ..... @qrr_e UQXTN_v 0.10 1110 ..1 00001 01001 0 ..... ..... @qrr_e FCVTN_v 0.00 1110 0.1 00001 01101 0 ..... ..... @qrr_hs +FCVTXN_v 0.10 1110 011 00001 01101 0 ..... ..... @qrr_s BFCVTN_v 0.00 1110 101 00001 01101 0 ..... ..... @qrr_h diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index d4d19c9caaf..1c454a37f41 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -8975,6 +8975,24 @@ static ArithOneOp * const f_scalar_uqxtn[] = { }; TRANS(UQXTN_s, do_2misc_narrow_scalar, a, f_scalar_uqxtn) +static void gen_fcvtxn_sd(TCGv_i64 d, TCGv_i64 n) +{ + /* + * 64 bit to 32 bit float conversion + * with von Neumann rounding (round to odd) + */ + TCGv_i32 tmp = tcg_temp_new_i32(); + gen_helper_fcvtx_f64_to_f32(tmp, n, tcg_env); + tcg_gen_extu_i32_i64(d, tmp); +} + +static ArithOneOp * const f_scalar_fcvtxn[] = { + NULL, + NULL, + gen_fcvtxn_sd, +}; +TRANS(FCVTXN_s, do_2misc_narrow_scalar, a, f_scalar_fcvtxn) + #undef WRAP_ENV static bool do_gvec_fn2(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn) @@ -9078,6 +9096,7 @@ static ArithOneOp * const f_vector_fcvtn[] = { gen_fcvtn_sd, }; TRANS(FCVTN_v, do_2misc_narrow_vector, a, f_vector_fcvtn) +TRANS(FCVTXN_v, do_2misc_narrow_vector, a, f_scalar_fcvtxn) static void gen_bfcvtn_hs(TCGv_i64 d, TCGv_i64 n) { @@ -9647,68 +9666,6 @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode, } } -static void handle_2misc_narrow(DisasContext *s, bool scalar, - int opcode, bool u, bool is_q, - int size, int rn, int rd) -{ - /* Handle 2-reg-misc ops which are narrowing (so each 2*size element - * in the source becomes a size element in the destination). - */ - int pass; - TCGv_i64 tcg_res[2]; - int destelt = is_q ? 2 : 0; - int passes = scalar ? 1 : 2; - - if (scalar) { - tcg_res[1] = tcg_constant_i64(0); - } - - for (pass = 0; pass < passes; pass++) { - TCGv_i64 tcg_op = tcg_temp_new_i64(); - NeonGenOne64OpFn *genfn = NULL; - NeonGenOne64OpEnvFn *genenvfn = NULL; - - if (scalar) { - read_vec_element(s, tcg_op, rn, pass, size + 1); - } else { - read_vec_element(s, tcg_op, rn, pass, MO_64); - } - tcg_res[pass] = tcg_temp_new_i64(); - - switch (opcode) { - case 0x56: /* FCVTXN, FCVTXN2 */ - { - /* - * 64 bit to 32 bit float conversion - * with von Neumann rounding (round to odd) - */ - TCGv_i32 tmp = tcg_temp_new_i32(); - assert(size == 2); - gen_helper_fcvtx_f64_to_f32(tmp, tcg_op, tcg_env); - tcg_gen_extu_i32_i64(tcg_res[pass], tmp); - } - break; - default: - case 0x12: /* XTN, SQXTUN */ - case 0x14: /* SQXTN, UQXTN */ - case 0x16: /* FCVTN, FCVTN2 */ - case 0x36: /* BFCVTN, BFCVTN2 */ - g_assert_not_reached(); - } - - if (genfn) { - genfn(tcg_res[pass], tcg_op); - } else if (genenvfn) { - genenvfn(tcg_res[pass], tcg_env, tcg_op); - } - } - - for (pass = 0; pass < 2; pass++) { - write_vec_element(s, tcg_res[pass], rd, destelt + pass, MO_32); - } - clear_vec_high(s, is_q, rd); -} - /* AdvSIMD scalar two reg misc * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 * +-----+---+-----------+------+-----------+--------+-----+------+------+ @@ -9780,15 +9737,6 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) rmode = FPROUNDING_TIEAWAY; break; case 0x56: /* FCVTXN, FCVTXN2 */ - if (size == 2) { - unallocated_encoding(s); - return; - } - if (!fp_access_check(s)) { - return; - } - handle_2misc_narrow(s, true, opcode, u, false, size - 1, rn, rd); - return; default: unallocated_encoding(s); return; @@ -10101,16 +10049,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) } handle_2misc_reciprocal(s, opcode, false, u, is_q, size, rn, rd); return; - case 0x56: /* FCVTXN, FCVTXN2 */ - if (size == 2) { - unallocated_encoding(s); - return; - } - if (!fp_access_check(s)) { - return; - } - handle_2misc_narrow(s, false, opcode, 0, is_q, size - 1, rn, rd); - return; case 0x17: /* FCVTL, FCVTL2 */ if (!fp_access_check(s)) { return; @@ -10160,6 +10098,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) default: case 0x16: /* FCVTN, FCVTN2 */ case 0x36: /* BFCVTN, BFCVTN2 */ + case 0x56: /* FCVTXN, FCVTXN2 */ unallocated_encoding(s); return; }