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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434d527eeedsm35050045e9.19.2024.12.04.12.27.34 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 04 Dec 2024 12:27:35 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , "Michael S. Tsirkin" , Peter Maydell , Laurent Vivier , Mark Cave-Ayland , Alistair Francis , Anton Johansson , Zhao Liu , "Edgar E. Iglesias" , David Hildenbrand , qemu-s390x@nongnu.org, Max Filippov , Paolo Bonzini , Nicholas Piggin , qemu-arm@nongnu.org, Thomas Huth , qemu-riscv@nongnu.org, Alistair Francis , qemu-ppc@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 10/20] target/microblaze: Implement CPUClass::datapath_is_big_endian Date: Wed, 4 Dec 2024 21:25:52 +0100 Message-ID: <20241204202602.58083-11-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241204202602.58083-1-philmd@linaro.org> References: <20241204202602.58083-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Implement the MicroBlaze datapath_is_big_endian() handler, returning the value of the ENDI bit. Signed-off-by: Philippe Mathieu-Daudé --- target/microblaze/cpu.h | 2 ++ target/microblaze/cpu.c | 11 +++++++++++ 2 files changed, 13 insertions(+) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 3e5a3e5c605..dd6b61b34ba 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -412,6 +412,8 @@ void mb_tcg_init(void); /* Ensure there is no overlap between the two masks. */ QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK); +bool mb_cpu_datapath_is_big_endian(CPUState *cs); + static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 710eb1146c1..3a0e5713415 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -26,6 +26,7 @@ #include "qapi/error.h" #include "cpu.h" #include "qemu/module.h" +#include "sysemu/hw_accel.h" #include "hw/qdev-properties.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" @@ -119,6 +120,15 @@ static bool mb_cpu_has_work(CPUState *cs) return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } +bool mb_cpu_datapath_is_big_endian(CPUState *cs) +{ + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + + cpu_synchronize_state(cs); + + return !cpu->cfg.endi; +} + static int mb_cpu_mmu_index(CPUState *cs, bool ifetch) { CPUMBState *env = cpu_env(cs); @@ -447,6 +457,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) &mcc->parent_phases); cc->class_by_name = mb_cpu_class_by_name; + cc->datapath_is_big_endian = mb_cpu_datapath_is_big_endian; cc->has_work = mb_cpu_has_work; cc->mmu_index = mb_cpu_mmu_index; cc->dump_state = mb_cpu_dump_state;